Research On Relieving The Aging Of Integrated Circuits Caused By NBTI Effect

The level of transistor fabrication technology continues to improve,its size continues to shrink,the performance of integrated circuits has been greatly improved,and the manufacturing cost has also dropped significantly,but at the same time,the physical defects of transistors have been amplified,resulting in the integration of integrated circuits.The reliability problem has become very serious.If the transistor manufacturing process size reaches 45 nm,the aging of the circuit caused by the Negative Bias Temperature Instability(NBTI)effect will become a reliability issue that circuit designers are mainly concerned with.This paper studies how to mitigate the reliability of integrated circuits caused by the NBTI effect.The specific work is as follows:Firstly,it introduces the rapid development of semiconductors in recent decades and the background of integrated circuit aging and several critical factors that cause aging of integrated circuits,and analyzes the NBTI effect from the Nanoscale manufacturing process level,which will lead to the aging of circuit integration.Secondly,three classical models for predicting NBTI effect-induced circuit ageing are introduced in detail:static NBTI effect prediction model,dynamic NBTI effect prediction model and long-term NBTI effect prediction model.According to the static NBTI effect prediction model based on reaction-diffusion mechanism and dynamic NBTI effect prediction model,the existing classical schemes for mitigating NBTI effect-induced circuit ageing and each classical model are compared.Advantages and disadvantages of the scheme.Thirdly,when classical gate replacement(GR)combines with input vector control(IVC)method to alleviate circuit ageing,it first uses IVC method for critical gates(logic gates which are easy to ageing and have a great impact on the delay variation of the whole circuit),then GR method is used for critical gates which IVC method can't alleviate.Although this method can reduce the area overhead,ignoring GR method will change the output of critical gates,so that the critical gates which have been alleviated by IVC method are in the state of pressure again,resulting in unsatisfactory optimization effect of the circuit.In order to solve this problem,this paper proposes to judge whether the critical gates are GR protective(whether they can be protected by gate replacement),replace the critical gates which are GR protective first,and then use IVC method for critical gates which are not GR protective,which can not only avoid the interference between the two methods,but also improve the protective effect of IVC method for large-scale circuits.Finally,this paper uses the ISCAS85 reference circuit to compare with the existing scheme.The experimental data show that the average delay improvement rate of the aging mitigation of the integrated circuit is 45.85%,which is 20.24%higher than the existing scheme.The existing program has increased by 1.9%.This article sacrifices a small area overhead for better optimization.Figure[32]Table[9]Reference[52]...