Jointly Mitigation Of Multiple Aging Effects In Nanoscale Integrated Circuits

With the advances in integrated circuit technology, the aggressive scaling down technology has largely improved the integration level and function of integrated circuit. However, it also has brought more challenges to the reliability of circuits. One of these challenges is circuit aging on which researchers have pay more and more attention. Nowadays, main research work concerning to circuit aging includes two aspects, which are aging modeling and aging optimization for the silicon-based MOS transistors and integrated circuits. When circuits are processed below 45nm technology, the shrinking silicon feature size brings in the use of high-k gate dielectric in order to alleviate the increasingly serious phenomenon of gate leakage current. With the introduction of high-k materials, the influence of PBTI on the transistor gets more researchers’ attention, and joint optimization with other aging effects is lacking. This dissertation focuses on joint optimization of the circuit aging effects in high-k gate dielectric MOS transistors.With the silicon feature size aggressively shrinking, high-k/metal gate is introduced to meet the industrial requirement of low leakage power. However, it will significantly exacerbate the Positive Bias Temperature Instability (PBTI) and Hot Carrier Injection (HCI) effect of NMOS transistor below 45nm CMOS process, which will increase the threshold voltage and degrade circuit performance. In this thesis, a brand new PBTI and HCI aging model is proposed jointly considering the stacking effect of transistors on input signal probability and the switching activity of transistors in series, then a W-value is defined and the W-value based input reordering approach is presented to co-mitigate PBTI and HCI induced circuit aging. Experimental results show that, compared to the actual value simulated by HSPICE, the average error of the previous model is 3.9%, the error of the proposed model can be reduced to 1.4% on average. The lifetime of logic gates can increase by 11.7% on average when the proposed input reordering method is used.In high-k material gate MOS transistor, Positive Bias Temperature Instability is getting worse. Previous optimization only focusing on NBTI effect and ignoring the PBTI effect is not perfect. This thesis presents a simulation-based BTI analysis in basic gates (such as NAND and NOR) while considering the impact of input’s duty cycle as well as the impact of the stressed transistor location. The simulation results show that the impact of BTI is strongly gate dependent, When considering both NBTI and PBTI for basic gates, the results reveal that for a NOR gate the impact of NBTI is 2.19 X higher than that of PBTI; while for a NAND gate, PBTI impact is 1.27 X higher than that of NBTI, the opposite effects are presented for NBTI/PBTI ratio depending on the transistor topology. In this paper, using input reordering to jointly mitigate NBTI and PBTI induced circuit aging is proposed. Experimental results show that, taking into account NBTI and PBTI, the lifetime of the circuit can increase by 10.8% on average, the maximum can be increased by 17.3%.