The Research On Reliability Of Integrated Circuit Induced By NBTI

With the development of semiconductor manufacturing technology,the dimension of nanometer process continues to narrow.The reliability of CMOS integrated circuit has become one of the greatest challenges in the whole process design.Especially in 65 nm CMOS process and below,negative bias temperature instability effect has become an important factor for reliability of CMOS device.Exploring the aging effect of NBTI in integrated circuit and remitting aging problems induced by NBTI,Therefore,has become hot spot in the reliability research at home and abroad.The research based on NBTI-induced aging prediction and protection technology is aimed at easing aging effect in this dissertation.At present,the common practice about aging online prediction technology in integrated circuit is to make the combinational logic embedded in aging-sensor.The aging-sensor can predict integrated circuit aging.However,the way can only detect this error which has been or will soon produce in aging process.It cannot make an accurate evaluation to the aging condition of integrated circuit.The aging protection technology is usually based on NBTI's partial recovery feature in integrated circuits.When integrated circuit is in the standby mode,the aim of anti-aging can be accomplished by controlling circuit internal nodes.The corresponding solutions are different,which include input vector control technology,door replacement technology and transmission technology,etc.But these approaches also bring a certain amount of extra hardware overhead to integrated circuit.In this dissertation,a new method which can identify anti-aging critical gates by prioritizing logic gates was proposed in view of NBTI-induced aging prediction technology before silicon.The method aims to pinpoint critical gates which cause serious aging effect in the original circuit.The designer can make anti-aging design in the design phase according to the available information and guarantee that ultimate circuit still meet timing requirements after a period of NBTI effect.The proposed method is based on a static timing analysis framework and RAS aging model.The logic gates from the aging-sensitive of paths were preferred in the circuit,and then the path correlation was analyzed to identify critical gates.Compared with similar methods in the same conditions of experimental environment,experimental results on ISCAS benchmark circuits at the 45nm CMOS process showed that,not only the number of the critical gates can be determined lesser,but also the delay mitigation of critical path is increased by 9.93%in average.It effectively reduces the design cost of expenses and provides a reliable guide for anti-aging design in integrated circuits.