The Research Of NBTI-induced Integrated Circuit Aging Optimization Base On IVC And Gate Replacement Techniques

In the nanometer regime, circuit aging induced by negative bias temperature instability (NBTI) is a significant reliability concern for digital IC. NBTI will cause a shift in the threshold voltages, increasing the delay of PMOS devices, and resulting in degradation of circuit speed, potentially leading to a functional failure. It is one of the main objectives for aging design that mitigate the NBTI-induced delay degradation.Without considering the protectability of critical gate, which is affected by the input type of the critical gate, the existing NBTI-induced circuit aging optimization techniques based gate replacement (GR) cause some critical gates not to be protected, resulting in poor optimization result. In this dissertation, a kind of GR scheme is proposed to optimize the circuit aging, in which the protectability of critical gates is taken account when the critical gates are identified. By using the proposed scheme, it can be enhanced to improve the NBTI-induced delay degradation. Experimental results show that compared with the existing technique without the protectability of critical gate being considered, the proposed scheme has on average up to 4.69,7.04 and 10.12 times improvement on NBTI-induced delay degradation under timing margin 5%,10% and 15%. It is proved that the proposed scheme is very effective when it is used to improve the optimization result of GR technique.By combining input vector control (IVC) technique with GR technique to mitigate the NBTI-induced circuit aging, the optimal input vector selection technique had been proposed in the literature. The existing scheme selects the minimum NBTI-induced circuit aging vector to be the optimal input vector, which can’t be able to take full advantage of GR technique and IVC technique to optimize the NBTI-induced circuit aging. A new optimal input vector selection scheme is proposed in this dissertation, in which the pin type and logic value of the critical gates are considered. For the protectability pin and no protectability pin that with logic value 1, a vector that can result maximization of the total number of them is selected to be as the optimal input vector. The experimental results reveal that the proposed optimal input vector selection scheme can improve 12.11% of the optimization result compared with the existing scheme, proving the superiority used for mitigating the NBTI-induced circuit aging.