Study On GALS Interconnection And System Design

With the advancement of semiconductor process technology and the development of IP (Intellectual Property) core reuse technique, complexity and integration of SoC (System on Chip) increase rapidly. However, the improvement of synchronous circuit in performance has already approached the limit by now. In recent years, the advantages of asynchronous circuit over synchronous circuit have come out in many respects, such as low-power, low-noise, anti-jamming, modularization and no clock skew and asynchronous design method has become one of the most important research areas again. Still, lack of mature EDA (Electronic Design Automation) tools and difficulty in testing are the vital obstacles of asynchronous design. Consequently, the design technique of GALS (Globally Asynchronous Locally Synchronous) has been taken into account, which shares the virtues of both synchronous and asynchronous design method. In the GALS design, local modules may employ the IP which has been well designed, and the connection and communication among the modules can realized in the asynchronous way.Interconnected units and design technique were studied in the dissertation. The main researches and achievements are represented as follow.1) Network architecture,node structure and communication manner of network on chip (NoC) have been studied systematically. GALS model encapsulating synchronous function modules in the asynchronous interfaces has also been analyzed. Then, handshake protocol and state control of asynchronously encapsulated circuits have been discussed. The way of handshake in asynchronous circuits, work processes of four-phase and two-phase signal transmission protocol have been given. After that, single track and dual track codes adopted in data communication have been discussed. State configuration sequences of handshaking signal and data signal have been got finally.2) Key units of asynchronous interconnection and function modules in asynchronous system have been designed. The design of CMOS circuit of C-element and Set-C element has been discussed. Netlist and layout have been achieved with SMIC 0.18μm-standard CMOS technology in Cadence. Energy consumption, rising delay and falling delay of each key unit have been analyzed and compared, options under different conditions have also been given. CMOS circuit designs of function modules such as Fork, Join and Merge have been made based on the present technology, and these function modules constitute larger system with other circuits, so as to satisfy the logical function need of GALS system.3) Controllable and stoppable clock circuits have been designed to meet the demands of the GALS system. 5 kinds of clock circuits with different frequency regulating precisions cover the range from 200MHz to 2.4GHz. By comparing power consumptions and sizes, corresponding concrete applications have been given. Combination and configuration can be performed to reach equilibrium between power consumption and performance.4) The asynchronous interface circuits have been designed. Local modules can be encapsulated as nodes of GALS system by the way of handshake protocol circuit based on four-phase single-track protocol. STG (Signal Transition Graph) of synchronous to asynchronous read-write conversion interface has been established through the method of Petri net. After synthesized by Petrify software, interface circuit has been realized by HDL (Hardware Description Language). On the basis of accurate emulation, transistor-level basic building blocks of GALS system including asynchronous read /write conversion interface and stoppable clock have been designed in Cadence.5) GALS system model has been set up by means of synchronous design. With the use of EDA tools, function modules assisting system have been obtained by HDL. Synchronous function modules controlled by local clock have been encapsulated by asynchronous handshake protocol circuit, which have composed point to point GALS system. Then, results of software simulation and hardware emulation carried out in FPGA have verified the efficiency and correctness of this system. Asynchronous handshake protocol circuit has been realized in CMOS circuit. By encapsulating ALU comprising CMOS circuits with asynchronous handshake protocol circuits, GALS system comprising transistors has been formed. Function simulations for GALS systems implemented in Cadence have showed the correctness of the system.Preliminary results that are to lay the foundation for practical applications of GALS system have been obtained in this papers such as GALS system structure, asynchronous communication protocol, EDA-aid-design and transistor-level asynchronous encapsulated circuit, and GALS system. Meanwhile, the design technique of the asynchronous key circuits and the implementation method of GALS system have the instructive significance for the design of GALS system.