Research On Test Pattern Generation Of Asynchronous Circuit

There are some advantages of asynchronous circuits over synchronous ones: Power consumption, modularity, performance, and electro-magnetic compatibility(EMC). So far, some beneficial attempts have been taken on design of asynchronous circuits. However, an efficient and effective production test technique is the final hurdle of the mass application of the asynchronous circuits.In this dissertation, researches on stable state generation for asynchronous circuits are taken first. On the basis of stable state of asynchronous circuits, stable state functions and output functions are easily gotten, and then test patterns are generated by solving functions, or function test can be carried out. We present the method generating stable state of asynchronous circuits using boolean satisfiability, and also present some speedup strategies to improve the efficiency of the algorithm according to the feature of the circuits.In this dissertation, some beneficial researches on test pattern generation for asynchronous circuits are taken. The procedure of the test pattern generation based on state transition graph is that first generating the fault distinguishing vector and then getting the preset sequence of this distinguishing vector. Because the state transition graph of every fault circuit must be calculated, the computing workload of test pattern generation is also vast. Analyzing process for generating test pattern of asynchronous circuits further, we present an algorithm for test patterns generation of asynchronous circuits independent on state transition graph. In detail, using Boolean Satisfiability method, compute the CNF formula of the normal circuit and fault circuit under the speedup strategies such as selected main path, and get a fault distinguishing vector. Then the circuit is simulated and if all of gates are satisfied by the vector, this vector is the test pattern of the fault, otherwise, loops must be identified firstly, then seek the preset sequence from primary output to primary input or decide this fault can not be tested finally. Compared with the...