Research And Design Of A Low Noise And High Power Supply Rejection On-chip Low Dropout Regulator

With design and process of the integrated circuit, more and more of the circuit are integrated together.. Usually, a digital-analog mixed IC contains a number of different digital and analog circuit modules, they have the different requirements about power supply, so we need several different power management circuits.Using traditional LDO in digital-analog mixed IC, we need more chip pins and PCB area. What‘s more, the application engineers need to choose an external capacitor with specific ESR value range to guarantee LDO’ stability. In addition, due to the parasitic inductance of pins and PCB, off chip capacitor cannot respond to the changes of high speed and high precision analog circuits effectively in time.This paper adopted a new structure of LDO on the basis of comparison, analysis and research about traditional LDO and on-chip LDO. Adding a buffer stage and reducing the gain of error amplifier, make the on-chip LDO having a good stability. Adding the compensation circuit at the same time, LDO achieves the high power supply rejection ratio with low loop gain. In the end, under the TSMC 40 nm CMOS technology, I have completed the design and pre-simulation of on-chip LDO with low noise and high power supply rejection ratio and bandgap reference circuit.Using 2 nF capacitance on chip, the LDO can work steadily with 0~1 m A load current under 1.62 V~1.98 V power supply. And, its output equivalent noise is only 227 u V in 1 KHz~10 GHz frequency range. In addition, its PSR is 54.97 d B at DC and bigger than 30.78 d B at all frequency with no load current. Its PSR is 58.2 d B at DC and bigger than 31.08 d B at all frequency with 1 m A load current.