Font Size: a A A

Design And Research Of Ultra-low Power SAR ADC

Posted on:2019-07-28Degree:MasterType:Thesis
Country:ChinaCandidate:L H WangFull Text:PDF
GTID:2428330545990214Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
Nowadays,Analog-to-Digital Converter(ADC)is widely applied to wireless sensor network,portable instrument and wearable equipment.Especially,because the capacity of battery in implantable health care instrument is relative small,it's emergent necessity for low power ADC.Successive Approximation Register Analog to Digital Converter(SAR ADC)with characteristics of simple architecture,small area and without static power,become primary choice at low power ADC.The redistribution procedure at capacitor array occupies largest proportion of total SAR ADC's power,therefore,reducing the switching energy of capacitor array by modifying architecture and algorithm is main approach to reduce down the total power in SAR ADC.This paper research the low power SAR ADC which applied to implantable health care instrument,include mainly follow content:(1)behavioral simulation is performed in Matlab for calculating switching energy to investigate the energy of the capacitor array,propose the new switching algorithm base on this.with analysis obtain that its energy savings of 99.2%compared to the conventional switching technique.(2)Investigate the linearity of the capacitor array in this switching scheme at this situation when capacitor mismatch.analyze the nonlinearity model when every capacitor obey specific normal distribution,2000 run monte carlo demonstrate it's standard deviation of INLand DNL is fine.(3)Design a low power dynamic comparator,this is a one stage latch comparator,it can reduce down kickback noise and offset voltage by modifying architecture and trimming the parameter of transistor.(4)Apply the propose switching scheme,design corresponding digital control logic circuits,include timing,register array and decoder circuits.C2MOS D-flip-flop is adopted as elementary storage unit.The schematic is designed in 40nM CMOS technology in Cadence spectre.With 1.1 V supply,the total circuits consumed 870nW at 909.9kS/s and achieved an ENOB of 9.83 bits and a SFDR of 70.5 dB.And the figure of merit were 1.07fJ/con-step.The range of DNL is-0.32-0.32LSB while the range of INL is-0.34-0.34.The total result of simulation demonstrate that the designed SAR ADC fulfil good performance.
Keywords/Search Tags:SAR ADC, ultra power, capacitor array
PDF Full Text Request
Related items