Research On Key Technologies Of Ultra-low Power RF Receiver

With the continuous development and innovation of wireless interconnection chips used in the Internet of Things(Io T),Io T devices such as wearable medical and implantable vital sign detection have been widely used in biomedical,industrial monitoring,and short-range wireless communication fields,and has attracted wide attention.This dissertation mainly involves the design and research of related circuits of ultra-low power RF receivers.The main research contents are as follows:1.The Overall Scheme Design of Ultra-low Power RF Receiver Chip: First,analyze and compare the structure of the low-power RF receiver chip,and then use the on-chip tapped-capacitor resonator based on the 2.4 GHz frequency band,which saves the chip area and solves the power consumption problem of the receiver's active front-end.In addition,a harmonic-rejection complex filter based on the principle of the M-path filter is proposed.The complex filter can effectively improve the power consumption of the baseband filter through the off-chip clock control.The simulation results show that the power consumption of the proposed receiver is only 271 ?W.2.Design of RF Front-end: The designed RF front-end mainly includes a tapped-capacitor resonator,a quadrature double-balance passive mixer,and a "windmill" frequency divider.First,the tapped capacitor resonator is a high-Q network resonating at 2.4 GHz,which is used to obtain the maximum power from an antenna with an internal resistance of 50 ?while transmitting the maximum voltage to the quadrature passive mixer.Secondly,the RF voltage signal is amplified by the resonator and then down-converted by a quadrature double-balance passive mixer.At the same time,the "windmill" frequency divider and drive circuit are used to provide accurate quadrature differential local oscillator signals for the mixer.3.Design of Reconfigurable Harmonic-Rejection Complex Filter: First analyze the equivalent model of the quadrature M-path filter circuit to understand its input impedance characteristics.Then a low-voltage IF amplifier is used to isolate the three-stage cascaded quadrature 8-path filter.Secondly,the 8-phase clock generator provides switching clock control for the quadrature 8-path filter.Finally,a three-stage cascaded 8-path complex filter is used to improve the harmonic rejection and in-band flatness performance of the overall filter.The test results show that the overall power consumption of the proposed harmonic rejection complex filter is 14.5 ?W,the bandwidth is 1.8 MHz,and the third and fifth harmonic suppression are 14 d Bc and 33 d Bc,respectively.4.Schematic,Layout Design and Simulation Verification: The 55 nm CMOS process is used to complete the schematic and layout design of the receiver system,and the RF front-end module of the ultra-low power RF receiver system(tapped-capacitor resonator+mixer),the reconfigurable harmonic-rejection module,and the overall receiver are simulated.Finally,the performance of these modules is summarized and compared with the current research status abroad.