Research In Low-power Circuit Of The Uhf Rfid Tag Chip

Radio frequency identification (RFID) technology provide a method to capture information automaticly, accurately and flexibly. With the development of information technology, RFID's applications increase rapidly and widely. RFID will become one of the fundamental technology in the future information society.The fundamental theory and link layers of ultra high frequency (UHF) RFID technology are discussed in this dissertation. The key design parameters of the UHF RFID tag are analyzed and how to design a low cost low power UHF RFID tag chip is studied.Firstly, The N stages voltage-doubler rectifier is studied and the analysis models with equations are built. The important parameters of RF front end, such as RF-DC power conversion efficiency, rectifier input impedance and working bandwidth of the chip, can be derived from the equations.Secondly, in order to get low cost and high performance chip, a schotttky diode using standard CMOS process is designed and fabricated. The simulation model is built based on the test result.According to the low power consumption requirement of tag chip, the new architecture of several building blocks such as voltage reference, data recovery, clock generator of tag chip is explored and realized for optimization in power supply rejection, power consumption, etc. New circuit architectures, such as voltage reference base on subthreshold and voltage reference base on switch capacitor circuit, are designed.In the end, a sample tag chip based on EPC C1G2 protocal is designed and fabrcated based on the optimized architecture with tow input RF channels and n bits frequency adjusted oscillator.