A Study Of 10 Bit 20KSPS 0.6V Ultra-low Power SAR A/D Converter

With the decrease of the CMOS process size, the digital circuit has achieved rapid development. The digital age is gradually coming. As the bridge between analog world and the digital world, AD converter is playing an irreplaceable role. With the continuous development of technology in the field of ADC, all kinds of ADCs which meets different needs were born. Successive approximation ADC(SAR ADC) with moderate conversion accuracy, moderate conversion speed has attracted much attention and research from its inception due to the its simple structure, low power, small chip area. Process improvement has brought a bigger challenge to analog circuit design. Because it doesn’t require linear gain blocks, SAR ADC is more suitable for process of the evolution route compared with other types of ADC. In recent years, SAR ADC with its unique advantages has become the new hot spot and has been widely studied in low power applications.A 10 bit ultra-low power successive approximation ADC is designed in the thesis. First, with the comparative study and analysis of the types of the successive approximation ADC, a relatively low-power charge redistribution type structure has been adopted. After doing some research about the structure of the capacitive conversion network and the capacitor switching procedure, a novel energy-efficient capacitor switching procedure is proposed. The scheme realizes the reuse of the terminal capacitance so that the switching energy of the capacitance array decreases because of the smaller capacitor area. Through the analysis of Matlab model, the area and the power consumption of capacitor array have been optimized compared with the conventional capacitor switching procedure, respectively 75% and 95.3%. At the same time, based the features of the novel energy-efficient capacitor switching procedure, bootstrapped switch and the basic dynamic latch comparator are used in the ADC. By analyzing the sampling switch charge injection, nonlinearity, the noise and dynamic offset of comparator, etc., we made corresponding optimization in each module.Finally, we carried on the simulation after layout. The core area is 0.43mm×0.38 mm, and the total area including pad is 1.2mm×1.2mm. At 0.6V supply voltage and 20.8KSPS, the ADC achieves SNDR of 61.8dB, SFDR of 70.48 dB and consumes 88 nW. The FOM of the SAR ADC is 4.2fJ/conversion-step.