Research And Design Of A Low Voltage And Low Power Analog To Digital Converter

Low power analog-to-digital converters are applied in most of varied kinds of battery-supplied portable electronic devices, e.g., mobile phones, panel computers, intelligent wearable devices and hand-held medical devices. To extent the life duty of those battery supplied devices, power dissipation of the mounted chips should be as low as possible; Meanwhile to meet the demands of multi-channels sampling applications, more than one analog input channel should added to the ADC chips.To implement such a low power multi-channels high performance ADC, a research is carried out and some strategies have been proposed as follows:(1). Low cost low power ADC architecture: By comparing advantages and disadvantages of different ADC architectures, SAR ADC architecture is chosen for its inherent features of low cost and low power. Meanwhile low power supply strategy is also taken. This chip is implemented by a CMOS 0.35μm technology. The standard supplied voltage of this technology is 3.3V, and to reduce the power dissipation of the system, a lower supply voltage is adopted. The minimum supply voltage is reduced from 3.3V to 1.8V, so the whole power dissipation can be reduced about 45%. As the threshold voltage of MOSFETs are not changed when lower down the supply voltage, it’s no longer an easy task when design MOS switches, comparators and bias circuits, etc.(2). Low cost and low power segmented charge-sharing DAC architecture is designed for the implementation of the SAR ADC. Charge-sharing DAC is implemented by using capacitor array architecture, so there is no static power dissipation but can match well. The segmented DAC architecture used in this design can further reduce the area of the overall capacitor array, so lower cost and lower power dissipation can be achieved.(3). To achieve low power and high performance, a regeneration latch comparator with a rail to rail input stage is designed. 1-to-1 current mirror bias reusing technique and sub-threshold technique are used to implement the rail to rail stage, which can reduce the power dissipation and the offset voltage of the comparator at the same time. A large Hysteresis voltage is designed in the regeneration latch stage, which can eliminate the turning errors of a comparator caused by the kickback noise, so the comparator can be more robust.The designed ADC chip is an as low as 1.9V supplied 4 channels, 10 bit, 300 ksps low power successive approximately registers analog-to-digital converter(SAR ADC) as measured. The die area of this chip is about 1.23mm2, and is implemented by using CMOS 0.35μm technology. The test results indicate that the power dissipation is only 200μW at a 2V single supply and a 166 kspssampling rate. And the calculated SNR is 58.25 dB, SFDR is 60 dB, INL and DNL are less than0.2LSB, ENOB is 9.4bit and FOM is 4.9pJ/conversion-step.