Research And Design Of Phase Locked Loop In CMOS Technology

Phase locked loop(PLL),which provides the local oscillator signal for wireless transceiver,determines the power consumption and bit error rate of wireless transceiver.Therefore,it is essentially important to design a low spur and low noise PLL in wireless transceiver system.Communication frequency band resources are becoming scarcer.Data security problems are growingly prominent.The 2.4 GHz ISM band can no longer meet people's requirements.Meanwhile,the demands for non-standard PICO net networking and medium-low speed business communication are getting stronger.In view of these problems above,a custom low power wireless communication project in the 3 GHz band emerges,and PLL is one of the important modules.A low spur and low noise charge-pump PLL is designed in this thesis.In order to prevent the pulling effect of power amplifier,the output frequency of charge-pump PLL is designed to be 6 GHz.After frequency division,four orthogonal output signals with frequency of 3 GHz can be obtained.The proposed charge-pump PLL is designed in 130 nm CMOS technology.Simulation results show that the charge-pump PLL achieves-109 dBc/Hz phase noise at 1 MHz offset of 6.016 GHz with a power consumption of 9.866 mW and reference spur of-64 dBc.In summary,the proposed charge-pump PLL meets project specifications.In order to solve the problem that the voltage controlled oscillator(VCO)is sensitive to supply voltage,a low dropout regulator(LDO)is used to supply the VCO,to reduce power supply voltage fluctuations and avoid the deterioration of PLL's spur.In a classical PLL,the noise power of phase detector and charge pump is multiplied by N2 at the output end due to the existence of the divider-by-N in the feedback path.As a result,low in-band phase noise can not be achieved.In order to break this bottleneck,a low phase noise sub-sampling PLL is designed.The sub-sampling PLL is composed of a core loop and a frequency locked loop.When the sub-sampling PLL is in locked state,the frequency locked loop stops working and there is no divider in the core loop.Therefore,extremely low in-band phase noise can be achieved.In order to improve the output spur of the sub-sampling PLL,a reference buffer with adjustable duty cycle is designed.Dummy samplers and self-biased isolation buffers are used to minimize the spur even further.Transient work process of the sub-sampling PLL is analyzed.Consequently,settling time can be reduced by increasing the output current of charge pump in frequency locked loop.The proposed sub-sampling PLL is designed in 180 nm CMOS technology.Post-layout Simulations indicate that the sub-sampling PLL has reached-123.5 dBc/Hz in-band phase noise at 1 MHz offset of 2.4 GHz with a power consumption of 6.96 mW and reference spur of-82.5 dBc.Moreover,the proposed sub-sampling PLL can remain stable from disturbance with a settling time of 3.8 us.