Design Of Charge Pump Phase Locked Loop And The Optimization Of Phase Noise

The paper describes the history, development and application in briefly, then, analyzes the basic principle of the charge pump PLL. It also introduces and compares some theories of PLL's phase noise. The paper gives a design of third order CPPLL and analogs it in detail. This PLL referred there is used in LVDS clocks, whose output frequency is from 10MHz to160MHz. It can be used in high speed LVDS system because the inter VCO has 7 order delay cell with 7 phases output standThe design method of Top to Down is used, which is from the system level design of charge pump PLL to the transistor level design of each block in PLL. Firstly, we get a linear continuous phase domain transfer function model by regard the charge pump PLL as a continuous and linear system. In the meantime, In order to prove the charge-pump phase-locked loops at the system level, the paper establishes a behavioral model in simulink. The behavioral model includes nonlinearity and discrete-time nature of charge-pump phase-locked loops, and then the behavioral model is used to simulate charge-pump phase-locked loops at the system level. Secondly, after each block's specification is decided, detailed design and simulation of these blocks are completed including Voltage Controlled Oscillator (VCO), Phase Frequency Detector (PFD), Charge Pump, Low Pass Filter (LPF), based on the 0.18μm Mixed-Mode and RFCMOS process technology of HJTC. In the meantime, two methods are used to improve the phase noise of VCO. Finally, the charge pump PLL system consisted by these blocks is simulated under different process, temperature and power voltage. From the simulation results, each block and the whole PLL system have obtained the design specifications.The achievement of this paper will provide lots of useful guides and references on the design of system and module level in PLL circuit also include the analysis and simulation of phase noise.