The Design Of A 20GHz Charge Pump PLL Based On TSMC90 Process

The demand for data transmission rate of wireless communication network has promoted the research and development of the 60 GHz short-range ultra-high speed wireless communication technology.The millimeter-wave wireless communication system is mostly based on Ga As,Si Ge and other processes,but the cost is so high which limits its development.The continuous improvement and maturity of silicon-based CMOS process make it possible to implement a wireless transceiver system based on the CMOS process.On the basis of the 60 GHz wireless transceiver system,this research focuses on the optimization of phase noise and reference spurs,and studies a high-performance 20 GHz integer frequency synthesizer.Firstly,compared with other different types of PLL,this research selects charge pump phase locked loop(CPPLL)due to its high performance,and also provides a design method of the loop parameters in the fourth-order fully differential PLL.Then the main circuit modules in the PLL are analyzed,including analyzing and discussing on the influencing factors of current loss in the fully-differential charge pump and expression of equivalent output current noise;Considering Q of the resonant circuit and optimization of contribution of the tail current source using mixing principle,LC-VCO is discussed;in order to ensure the reliability of feedback loop,CML-DFF is analyzed mainly from the perspective of the working principle and the relationship between frequency-locked range and injection amplitude,and the method that can broaden the lock range of CML is also provided;considering the characteristics of high precision and low phase noise of the frequency division link,a retiming unit is added to the output.In order to effectively reduce the chip area,a capacitor doubler circuit is added.Then,the function expression of equivalent output noise of each circuit module is mainly analyzed and discussed,and the concrete function expression of the contribution to the overall output noise is also provided,thus obtaining the comprehensive optimization design of phase-locked loop output phase noise.Meanwhile,the concrete expression of current-induced reference spur is analyzed in detail and the design method to achieve low reference spurs is put forward accordingly.Considering the influence on loop stability,phase noise and reference spur,some tentative suggestions are put forward for choosing the loop bandwidth and the out-of-band poles.Finally,a high-performance 20 GHz frequency synthesizer is designed based on the TSMC90 nm CMOS process.The results show that the VCO can achieve 19?22GHz tuning range,and the lock range of CML-DFF is 1?30GHz,and the phase noise of the frequency synthesizer are-94.06@1k Hz,-103.2@10k Hz,-101.9@100k Hz and-99.92 d Bc/Hz@1MHz,and the output reference spur is-56.1d Bc,all meet the system performance requirements.