Study On The Anti-Radiation Placement And Routing Algorithms For FPGA

In order to shorten the development cycle and reduce the cost,researchers widely use SRAM-based FPGA to research modern satellite.However,in space radiation environment,SRAM-based FPGA is more susceptible to single event effects and other"soft error" than other types of programmable logic devices,such as Application Specific Integrated Circuit and the fuse type FPGA.U.S.National Geophysical Data Center statistics show that from 1971 to 1986,there are 39 satellites in geostationary orbit anomalies abnormal,and the single-particle radiation-induced failures accounted for about 70%of the total.Therefore,it has become an important research topic that enhancing the soft error tolerance ability of the FPGA and improving the system reliability.Traditional methods of FPGA resistance to soft error are all focus on hardware development,leading to area increasing and power consumption of the system.In order to overcome the shortcomings mentioned above,this paper proposed a new FPGA fault-tolerant method——Anti-VPR placement and routing algorithm.This paper firstly analyzed the formation mechanism of the soft error and made error modeling on FPGA general structure.Secondly,a FPGA oriented method for calculating the probability of error propagation and a placement algorithm that could resist FPGA soft error were proposed.Thirdly,to solve the delay problem of the critical path brought by Anti-VPR placement algorithm,the improved delay placement algorithm was proposed.Finally,based on the previous work,an anti-radiation routing algorithm was proposed,and its reliability and validity have been verified through simulation experiments.Compared with the original algorithm,the new proposed algorithm in this paper has made improvements in three aspects.Firstly,by analyzing the node error rate and the fault propagation probability of each bounding box of each,an anti-radiation placement algorithm was proposed.Secondly,the computation of each connect key factors is not accurate in FPGA timing-driven placement algorithm,so the placement of each critical path delay was not necessarily a minimum and the placement is not necessarily the best.This paper introduced a delay precision factor in placement algorithm in order to better measure the timing quality of each placement and reduce the critical path delay final placement.Thirdly,in order to reduce the impact on SEU routing algorithm,we also increased the anti-radiation disciplinary factor to minimize the number of open-sensitive bits.Experimental results show that,compared with the original algorithm,our improved algorithm can reduce the number of sensitive 21.1%and ensure critical path delay remain stable.