Research On Test Data Compression Methods In SOC Based On Full Scan Design

With the continuous improvements in the semiconductor manufacturing technology,the integrated circuits is becoming more and more complex,and tens or even hundreds of millions of transistors can be integrated into a silicon die,which promotes the advent of System-On-a-Chip(SOC).The design of SOC mainly adopts the technique of reusable Intellectual-Property(IP)cores,and maps the whole system to a single chip,so it can shorten the time to market,and lower the cost of chips.SOC can greatly reduce the size of products and improve the performance of the system by reducing the delay between chips.Therefore,it has been widely used in many industrial fields in recent years.With the increasing of the IP core number,and the improvement of performance,the test data,test power and the difficulty of the test has increased together,so the SOC test plays an important role in product development.The accuracy of the test is directly related to the quality of the merits of electronic products.It has been the primary problem for SOC test to reduce the test time and lower the cost at the same time.This thesis analyses the main problems in the SOC test based on the study of the SOC test methods,test compression techniques and test structures,and focuses on the problem of big test data and time-consuming,proposed two SOC data compression algorithm based on the scan chain,the main research results are as follows:(1)For test data to a compatible,a test data compression scheme based on mixed compatible date blocks is presented.In the scheme,binary code is used to express the test data which are compatible with reference data,and eligible test data are compressed with one-bite compression,which are improved compression radio.The circuit structure of decoder with a finite state machine(FSM)and a cyclical scan register(CSR)was proposed.Simulation on a standard circuit ISCAS89 test,test results show that the algorithm is better than another enco ding improve the compression ratio.(2)Presents a run-encoding variable compression algorithm,In front of the data compression algorithm,the decoding circuit exists CSR.A test compression approach based on Variable-Run-Length code is proposed in this dissertation.Both runs of 0's and runs of 1's in test data stream are mapped to codeword so as to reduce the number of short runs and improve compression ratio.Simulation on a standard circuit ISCAS89 test set,test results show that the algorithm is bette r than traditional Golomb coding,VIHC coding and FDR coding encoding compression performance on better performance,test time and less occupied.