Research On Decomposition-based Test Stimulate Compression Methods For Digital Circuits

As the advanced circuit design and application of latest manufacturing technologies have enabled the integration of a large number of IP cores into the system-on-chip(SOC),ensuring the reliability and high quality of semiconductor products has remained the primary of SOCs testing.However,a large amount of test data are required to complete SOC testing.During test application,automatic test equipment transmits the test data to the SOC through test channels.Since the number of channels and their bandwidth is limited,the data transmission rate is directly affected.This not only extends test application time but also increases the test power dissipation.Testing problems related to time and power have become a hot topic in the testing field.One of the effective methods to solve it is the test stimulus compression.To enhance the compression efficiency of code-based methods,this dissertation mainly studies the test stimulus data preprocessing method based on decomposing.To achieve the goal of reducing test stimulus data volume,decreasing test application time,and lowering the scan-in test power dissipation,The main contributions of this dissertation are as follows:1)Firstly,an algorithm on column-wise reordering for the Hadamard matrix is proposed to decomposing a test set into a primary component set(PCS)and a residual component set(RCS)through transform.The PCS can be compressed on-chip,and the RCS replaces the original test set(OTS)as the encoded data.Compared with the OTS,the RCS can be compressed more effectively by code-based compressions.In addition,the correlation between the test patterns is utilized in the transform and decomposing,but the order of test patterns is never changed.Secondly,we designed a novel column-wise reordering algorithm for the RCS.This algorithm reduces the entropy of the RCS by determining the placement of each column one by one.Through theoretical analysis,we find that the entropy reduction of the RCS can further improve the code-based compression efficiency.For a large RCS,a reordering method can reduce the entropy of the RCS.This reordering problem is equivalent to an NP-hard problem,and the proposed algorithm can effectively solve this problem.Experiments on the Min Test set generated for parts of ISCAS'89 benchmark circuits show that the two algorithms can increase the average compression ratio for 7 code-based schemes by 19.91% in total,while the bestimproved compression ratio can reach up to 85.04%.Comparing compression ratios for the two algorithms before and after being applied,the difference between them is decreased,which indicates that the proposed algorithms are suitable for all kinds of code-based compressions.2)A pseudo-random transform and decomposing method is proposed for preprocessing a test set.This method constructs a pseudo-random matrix,which includes a vector obtained in the process of exploring the bit-stream characteristics of the test set,and pseudo-random sequences output by the linear feedback shift register(LFSR)circuit,and the result of an exclusive OR operation among these sequences.The matrix and the test set are subjected to matrix multiplication in math,that is,matrix transform.Each bit-stream in the test set can resolve its corresponding primary component(PC)through this transform.All PCs make up of a PCS in the order of their corresponding bit-streams.The difference between the PCS and the OTS is defined as the RCS.Aiming at the PCS compression,a simple structure test pattern decompressor is designed based on the LFSR.The code-based compressibility of the OTS can be transformed into the compressibility of the RCS.Considering that the primitive or non-primitive characteristic polynomials of the LFSR exits,two test pattern compression algorithms are designed based on pseudo-random transform and decomposing.Experimental results based on parts of the ISCAS'89 benchmark circuits and 7 common code-based schemes show that the two algorithms significantly improve the coding compression efficiency,and their compression effects are very close.This also shows that the pseudo-random transform and decomposing-based method is effective for processing the test set.3)A transform-decomposing preprocessing method is proposed based on the significant components of the test set.The research finds that the current matrix applied in transformdecomposing-based methods cannot fully reflect the primary characteristics of the test set.This affects the further improvement of the similarity between the test set and the PCS.Since the PCs in the PCS are derived from the transform matrix,this research uses the matrix as the key to solving the problem.After the proposed method classifies and clusters the bit-streams of the test set,significant components that can represent the characteristics of the test set are extracted.Under the condition of using these significant components to construct a matrix,the OTS can be decomposed into a PCS and an RCS through the matrix transform between the matrix and bit-streams mathematically.Aiming at the PCS compression,this dissertation designs an on-chip test pattern decompressor based on RAM parallel output.Compared with the OTS,the RCS has better coding compressibility.Combining the ISCAS'89 benchmark circuit and 7 common code-based compressions,the experimental results show that the highest compression ratio for the proposed method can reach 80.53% on average.Compared with the state-of-the-art transform-decomposing method,the average compression ratios for different code-based schemes are increased in the proposed method,where the largest increase is 5.27%of RL-Huffman code.4)A double-Hamming-distance-based 2D reordering method for a test set is proposed for the test set containing don't care bits(Xs).This method can effectively reduce the scan-in test power dissipation and compress the test patterns.In this method,the rows and columns in the test set are reordered,respectively,to cluster similar rows or similar columns close.Being different from other 2D reordering methods,the proposed method can place two rows contain more specified bits closer,and let two columns with more specified bits closer.This process gathers more Xs.Under the application of the minimum transition filling(MT-filling)scheme,the Xs are assigned by 0 or 1 to minimize the number of ”1-0” or ”0-1” logic state transitions.A small number of logic state transitions will bring low-frequency switching activities,which can not only reduce the scan-in test power dissipation but also facilitate test pattern code-based compressions.Experimental results based on Min Test sets of parts of ISCAS'89standard sequential circuits and 7 common coding compressions show that,compared with the state-of-the-art methods,our method reduces peak power consumption and average power consumption by 18.01% and 12.97%,respectively.In addition,the compression ratio for ASFDR code is increased to 73.76% on average.