The Design Of Embedded ADC Applied In DSP

As the development of digital technique,the design of ADCs in signal processing system is becoming more and more important.Nowadays,integrated circuits design follows the trends of low costs,small area and low power consumption,so ADCs in DSP with small area and low power consumption and high accuracy are highly developed and widely used.This thesis focuses on the design of embedded multiple channels 12 bits Analog-to-Digital Convert in DSP.Considering the trade-offs among power consumption,area,speed and channels,this ADC adopts the pipeline ADC structure including first nine stages with 1.5bits/stage and final stage with 3bits flash ADC.And the digital calibration techniques are applied to improve the accuracy of the ADC.The pipeline ADC includes the S/H,sub-ADC,MDAC,Voltage reference,clock generator and digital calibration circuit.The pipeline ADC transforms the system design requirements to each sub-stage.The thesis accomplishes circuits of the pipeline ADC according design requirements.The following techniques are taken: two-stage gain boosted amplifier to achieve high gain and high speed,the high-speed dynamic comparator with offset cancellation to keep low power consumption,improved bootstrap sample switches in S/H and MDAC to increase the linearity.Finally,the layout is designed based on SMIC 0.18?m six metals by the software Virtuoso.The ADC circuit is designed and validated by the software AMS of Cadence in Linux.Simulation results show that when the frequency of the input signal is 0.1MHz,the amplitude is 3V,the sampling frequency is 12.5MHz,the ADC achieves a SNR of 72.5d B,a SFDR of 81.8d B,a SNDR of 71.3 d B,and 11.55 bits of ENOB.The total power consumption is 67 m W.The area of the layout is 1×1.3mm2.All of these results meet the system requirements well.