Design Of14Bits50MHz Sampling Rate Pipeline ADC

With the rapid development of digital signal processing and communicationtechnology, analog-to-digital converter as the analog signal and the digital signalinterface is proposed ever-increasing demands, mainly for the design of high-speed,high-precision and low power consumption. Pipelined analog-to-digital converter(pipeline ADC) is the best compromise between high speed and high precision.Therefore, pipeline ADC power optimization design, system-level design of digitalcalibration and according to the circuit parameters provided by the system for circuitdesign are studied in detail.The non-ideal factors of the finite gain, the finite unity gain bandwidth, the offsetvoltage and the non-linear error, capacitor mismatch, the switch resistance error, KT/Cnoise and clock jitter noise etc. cause the decline in the performance of the pipelineADC. A detailed analysis of these factors and their Matlab models is setup to understandthe impact of various factors on the whole of the ADC. Based on this model, poweroptimization of the whole pipeline ADC design gives the lowest power consumption ofeach pipeline ADC structure combinations and various circuit sub-module circuit designparameters. In order to further reducing the power consumption and reducing CMOSprocess error, digital background calibration techniques based on pseudo-randomnumber, i.e. based on the pseudo-random input signal uncorrelated and itsautocorrelation characteristics, is used to extract linear errors of the pipeline ADC’sstages, and calibrate these errors in the digital domain.According to the result of Matlab simulation in certain CMOS technique, the14bit50Msps pipeline ADC consisting of two2.5-bit, ten1.5-bit and a2-bit is designed,using digital background calibration techniques of the former two stages, and the last2-bit used for digital calibration. In the Matlab model,1%capacitor mismatchintroduced, the simulation comparison shows that the algorithm makes the system DNL,INL improve0.25LSB and16.5LSB, SFDR improve13.4dB. Meanwhile, write verlogcode for circuit co-simulation, to achieve the same effect with Matlab simulation.Finally, in the light of circuit design parameters based on system simulation and using 0.35μm CMOS process, a pipeline ADC with digital background calibration is designed.And this ADC achieves0.175LSB DNL,1.625LSB INL,13.21bit ENOB,100.01dBSFDR and97.46dB THD by the overall ADC circuit simulation.