Pipeline ADC System Modeling And Sinmulation Based On Power Optimization And Digital Self-calibration Algorithm

With the rapid development of science and technology, especially the digital signal processing and communication system, as the interface of analog signal and the digital signal, analog-to-digital converter is proposed ever-increasing demands, mainly for the design of high-speed, high-precision and low-power consumption.Pipelined analog-to-digital converter have the best compromised capacity between high-speed and high-precision of various analog-to-digital converters. Therefore, a detailed analysis of errors and noises and their mathematic models of pipeline analog-to-digital converter are presented. Based on the process conditions, the stage-resolution theory and capacitor scaling-down technology are adopted, the optimal power consumption framework and design indexes of a 14-bit 10 MHz pipeline ADC are calculated. Meanwhile, a digital self-calibration algorithm aimed at eliminating the capacitor mismatch error and amplifier offset error of the calibration stage is presented. In this thesis, a 14-bit 10 MHz pipeline ADC based on the Matlab and Simulink which consist of twelve 1.5-bit stages and one 2-bit stage is designed. At the same time, the proposed digital self-calibration algorithm for the first 1.5-bit pipeline stage is adopted. Some capacitor mismatch error and amplifier offset error are imported in the behavioral modeling, and the availability and feasibility of proposed digital self-calibration algorithm are verified.Based on calculated optimal power consumption framework and design indexes, a 14-bit resolution 10 MHz sample rate pipeline ADC was fabricated in CSMC 0.5 μm one-poly three-metal CMOS process which occupying 2.26×3.05mm2 die area and consuming 308.96 mW at 5V analog power supply and 3.3V digital power supply. The static and dynamic measurements shows that, after calibration, the ADC achieves 14-bit linearity with +0.81/-0.91 LSB DNL and +1.47/-1.99 LSB INL. And the ADC achieves 79.61 dB SFDR and 72.83 dB SNDR for an input sine signal, and the ENOB achieves 11.81 bits.