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Design Of 4-channels 12 Bit 200MHz Time-interleaved Pipeline ADC

Posted on:2018-12-18Degree:MasterType:Thesis
Country:ChinaCandidate:S S LiFull Text:PDF
GTID:2348330533969470Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Pipeline ADC has a high precision and medium-speed sampling best compromise,but still faces the speed and precision that are close to the bottleneck and difficult to improve again.In this case,the best approach is to increase the number of channels to increase the input signal sampling frequency to meet performance requirements.This paper designs a 4-channel time-interleaved ADC,based on the SMIC 90 nm CMOS technic.The pipeline ADC has a precision of 12 bit,with a speed of 50 MHz,which enables the sample rate of 200 MHz.This paper analyzes the non-irrational features of the subclass module,including the non-linearity,charge injection and delay of comparator,and determines the specific solution.The subchannel pipeline ADC is used to form a 12 bit precision with a 10 1.5bit/stage and 1 Flash ADC serial output;The 4-channel pipeline ADC is sampled periodically,and get the final output of time-interleaved ADC by multiplexer.Through circuit simulation verification,the enob of pipeline ADC is 11.1 bit,when the signal of 3.1372 MHz is inputed,and the enob of four-channel time-interleaved ADC is 10 bit on the signal of 12.5488 MHz.However time-interleaved ADC has mismatch errors between different subchannels,especially the sampling time deviation impact.It not only reduce the precision of the output signal,but also increase the additional clock jitter.To reduce the loss of the overall ADC performance,This paper present the backstage calibration system based on LMS-FIR and interpolation filter.The desired reference channel is obtained by interpolation.The adaptive filter is used to adjust the mean square error between the reference channel and the channel to be calibrated by adaptive filtering.The pre-corrected circuit have 0.5% of offset,gain mismatch of 30 dB,the maximum sampling time deviation of 260 ps.After correction,the spurious performance is significantly reduced and the overall noise reduction is decreased,the SNR is 65.6 dB and enob is 10.6bit.The calibration effect is obvious with enob inproved by 3.6bit and the spurious performance decreased by 30.7 dB.
Keywords/Search Tags:time-inrterleaved, pipeline ADC, LMS-FIR, interpolation, digital background calibration
PDF Full Text Request
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