Low Power CMOS Pipeline ADC Circuit Design And Implementation

Analog-to-digital converters have been widely used in modern circuitand systems including wireless transceivers, CMOS image sensors and soon. Along with the new trends and continuous growth in wirelesscommunication market, converters with higher linearity, lower power andhigher sampling rate are in great demand.Digital integrated circuits have benefited a lot from the scaling ofsemiconductor feature size, more and more complicated and highperformance digital integrated circuits has been developed. However, dueto the scaling of supply voltage, the signal to noise ratio of analog circuitswould decrease. In order to maintain the SNR, larger sampling capacitorsshould be used. With a larger capacitor the current need to be increased todrive the capacitor which results in a higher system power consumption.This paper mainly focuses on low power design techniques of apipeline ADC. Non-idealities are carefully considered and techniques suchas sampling stage elimination, capacitor scaling, dynamic powerconsumption and dynamic comparators etc. are used.According to the dynamic test of the10bit20Msps pipeline ADC chip,we got an ENOB of8.53bits. The SNR, SFDR, SNDR and THD are55.12dB,59.19dB,53.13dB and57.49dB respectively.