Block-level Physical Design And Research Of ASIC Chips

With the rapid development of the integrated circuit industry, chip technology feature size shrinks rapidly to the nano level, and the function of the nanometer technology chip become more powerful. At the same time, it also brings many new challenges, such as multi-mode multi-corner increased timing convergence complexity, crosstalk effects on timing and antenna effect problems and so on. This is also the focus of the work of this paper.This paper introduced USB block’s synthesis and physical design with more than8 00000 gate level by a series of tools of Synopsys based on Samsung 28 nm process,it also introduced demo00 block’ s physical verification with a quarter of a million gate level by Calibre tool based on the same process. In the paper,it made a deep research on the Onepiece3 system,logic synthesis,timing constraints,data prepare,floorplan,placement,clock tree synthesis,route,static timing analysis and physical verification.It both introduced some problems and their solutions in the process of chip block-level’s logic synthesis and physical design,such as timing violation fixing,congestion, antenna effect, crosstalk, power and so on; meanwhile,it analyzed some problems in the process of chip block-level’s physical verification,and the most important part is LVS and their solutions.This paper also described how to solve regular repetitive problems efficiently by using Tcl script in order to reduce the trouble of iteration and save time.