Physical Design Of A Chip On NUCSoC

The convertion from gate-level netlists to layout is physical design, which bridges the chip design and manufacturing. Pyhsical design not only relates to the function of integrated ciucuit, but also relates to its performance and costs, the process includes: logic synthesis, floorplan, clocktree synthesis, routing-plan and physical verification.This paper proposed a method with low power consumption and timing convergence, which is based on the NUCSoc design. The proposed method includes three steps: firstly, according to the NUCSoc function, analysize the required timing in each clock domains and execute the logic synthesis; Secondly, prepare the required data and finish the floorplan, clocktree synthesis and routing plan operations; Finally, verify the layout, inculding the timing verification, power verification, floorplan rationality verification, DRC verification and LVS verification.According to the power requirment, this paper optimized the power in the following operations: adjust PAD/hard macro/soft macro locations, plan power network, insert buffer and optimize gate size of clocktree synthesis, set crosstalk parameters in the routing plan. The simulated results show that the proposed method has saved the power 10.92%.For timing optimization, set up the timing constraint firstly, analyze the factors which influence timing, and then execute the optimizing operations, which includes insert buffer, optimize gate size in the clocktree synthesis phase and the routing phase. Finally, gain the effective layout, which achieves the acquirement of setup time, hold time, max fanout, transition time and load capacitance. The simulation shows that the optimizing method has saved the timing 6%.The chip has been tested on ATE, and the testing results is 100MHz on the clock frequency, 199mW on core power consumption, 255mW on chip power consumption, 457 thousand equivalent logic gates and 2.4 mm×3.58 mm area. For a 640×480×14bit image, the data throughput of the chip can reach 100 frames per second, which meets the real-time requirement of the applications. These tested results show that the proposed methods in this paper are effective.