Logical Physical Synthesis And Verification Of GSM IC

GSM IC, as an ultra low cost base band chip, has major business values. At the same time, the successful logical physical synthesis and verification is one of the most important part of the whole chip design.This thesis focuses on the logical physical synthesis and verification of GSM IC, includes logical synthesis and scan insertion with Talus Design, floorplan, power plan, place and route, clock tree synthesis with Talus Vortex, STA with Primetime, Equivalence check with LEC, Layout Verificaiton with Calibre, IRdrop with Talus Rail.After logical physical synthesis&other fixes, all verifications are clean. From STA perspective, no violation in any modes, from layout verification perspective, all checks are clean, from formal verification point of view, codes and netlsits are equivalent, from IRdrop point of view, IRdrop results are within signoff limit. Finally, the chip achieved tape out and volume production.