Physical Design And Implementation Of Radiation-resistant MCU Chip

The high reliability,low cost,short design cycle and long service life of integrated circuits in complex radiation environments have always been one of the research hotspots in the field of microelectronics.This subject uses the radiation-hardened standard cell library of the 180 nm process to complete the semi-custom design process from the RTL code of the MCU chip to the GDS.Complete the post-simulation of radiation sequential cells,use Siliconsmart to extract the timing information of all cells in different environments and improve the library file.Through the Design Compiler,the gate-level netlist of the radiation-resistant MCU chip is synthesized,there is no violation of the setup time,and the chip is estimated to be nearly 120,000 gates,with a total power consumption of 150 m W.Use Formality formal verification tool to ensure that the RTL of the radiation-resistant MCU chip is equivalent to the gate-level netlist logic function.In order to improve the efficiency of layout iterative design,using an automated place and route process with a non-graphical interface,writing command scripts for each stage include import and floorplan,powerplan,standard cell placement and optimization,clock tree synthesis and optimization,routing and optimization and fix hold time.The MMMC analysis strategy is adopted for the complex working environment of the anti-radiation chip,the macro modules are arranged according to the data flow and the IO arrangement is completed,and the endcap cells is added to prevent the influence of process errors.Comprehensively consider the chip power consumption and the maximum current of the power supply port to plan the chip power network,adjust the margin of clock uncertainty and set the placement density of narrow channel cells to optimize timing.CTS chooses clock cells of moderate driving force and reasonably set the target skew and target transition to make the clock tree of good quality,design special via and add non-default winding rules,use high-level metal double width double space for the large fan-out part of the clock tree to effectively reduce crosstalk noise.After routing,conduct path crosstalk analysis and repair,optimize chip leakage power consumption,and perform DRC,antenna effect and timing check on the chip layout,there no violation path exists.Combine the custom map file and library file to export the correct layout,physical verification to ensure that the layout of the anti-radiation MCU chip is consistent with the circuit netlist.Static timing analysis uses Timing ECO scheme for timing repair,and finally there are no design rules,setup and hold time violations.The chip area is6000×5900?m~2,the number of instance units is about 130,000,about 150,000 connections,and the density is 76%.