Design And Verification Of 10 Gigabit Backplane Ethernet Physical Coding Sublayer

The Ethernet is a computer LAN based on the transmission of data frames. With the continuous development of Ethernet, it has extended to MAN and WAN from the original LAN. Regarded as the advanced technology in the Ethernet field, 10 Gigabit Ethernet bears great potential and promising prospects, but the domestic research is just in the initial stage. So the design of 10 Gigabit Ethernet is of great significance.Based on the analysis of function and design of 10GBASE-KR Physical Coding Sub-layer, the whole front-end design of PCS sub-layer is completed in this paper according to the IEEE Std 802.3ap protocol. Its main function is to send the data frames transmitted from MAC to PMA by adding check codes, encoding and conversion; and the data frames from PMA to MAC after converting, decoding and modification. There are many modules in PCS, such as CRC8 insertion and removal, 64B/66B encoder and decoder, scrambler and descrambler, gearbox and so on.Firstly, based on the serious study of IEEE Std 802.3ap protocol, this thesis anatomized the function and design of PCS sub-layer and put forward the design framework.Secondly, this thesis completed the design of each module with the method of top-down and modular design. As the specific module of Ethernet PCS sub-layer, CRC8 insertion and CRC8 removal support the error protection of data frames in the process of transmission, simplify circuit framework and ensure the continuous data transmission through hybrid algorithm of CRC8 checking code. With the method of logical operation,64B/66B encoder and 64B/66B decoder complete the data encoding and decoding process by dividing the design into two parts:one to confirm the type of input data, the other to operate following to the relevant rules. It reduces the circuit area and cost of the circuit compared with LUT method. Including dispatching and receiving channel, the gearbox, consisted of data conversion, asynchronous FIFO and control circuit, reduced the circuit area (with an extra 528 bit memory cell) and avoids the unsteady and delay of circuit effectively. Besides, the Finite State Machines mechanism was used in transmission circuit, receive circuit and synchronization-head detection as well as BER circuit to improve the work efficiency.Thirdly, this thesis presented the simulation and verification of PCS design. The test platform is set up based on the functional characteristics of PCS to complete the functional verification of the PCS design both in module level and system level, the loopback test, and the FPGA verification. The results indicated that all the designs meet the functional requirements. In addition, the logic synthesis of PCS is finished based on SMIC 40nm CMOS process, which proved that the service frequency of PCS can reach to 232.56MHz.