The Physical Design And Physical Verification Of FFT ASIC

Physical design is an important segment in the IC design, it will transform the RTL code on the logical level into physical layout which can be taped out, included are synthesis, placement and route, clock tree synthesis, physical verification and some other factors. A worthy physical design will not only influence whether the chip work well, but also have a great effect on the performance parameters and cost of production. With the rapid development of IC technology, system takes on higher complication, and the scale of chip is increasing, which highly challenge against back-end designer.Aiming at the very large chip area, the article summarizes a design process characteristic of timing closure, low-power, and excellent manufacturability, based on discussion of traditional physical design. Firstly, data preparation before synthesis. I mainly use Memory Compile to generate various files the memory needs, which requires coordination with later design process, constant iteration, to modulate aspect ratio and power line width of the memory, etc, thus getting reasonable parameter settings. Next,using Design Compile for physical synthesis. In order to reduce difficulty of subsequent timing closure, this stage increases time series cushion by tightening the constraints appropriately, which can result in a gate-level netlist of rational construction and sufficient margin. Then, to use IC Compile to design for floor-planning, placement, clock tree synthesis, routing, etc, as well as analyze and optimize functionality and performance,including modulating IO and the location of the macrocell, power resources network planning, crosstalk analysis and modulation of buffer while achieving clock tree synthesis and wiring, adopting Zroute engine to route, etc. Finally, to analyze design for manufacturing. This stage maily includes correction of antenna effect by upper jumper wire method; inserting standard cell filler; filling metal density; and manipulating physical verification of DRC, LVS, and antenna effect on layout, thus we can get a high-performance layout in which timing closure emerges, area and power consumption meet the standard.As the procedure introduced in this article proceeds, final FTT design adopts SMIC0.18 um 1P6M, the working frequency is 100 MHz, the power consumption is 420 mW, andthe area is 9528 um x 9528 um. The design has gotten through the validation of static timing analysis, DRC and LVS physical verification, post-layout simulation, etc, and has been also taped out.