The Design And Verification Of Memory Access Unit Of YHFT-DX High Performance DSP

Digital signal processors (DSPs), a class of embedded microprocessors optimized for digital signal processing, have become a key component in many multimedia appliances, communication devices, medical instruments, radar and other industrial products. Based on the design of Memory Access Unit of high performance DSP YHFT-DX, this thesis mainly discusses three points: Full-custom of critical circuit, logic synthesis and physical design of Acess Memory, and hierarchical verification of the design. The design is implemented with the combination of Full-custom and Semi-custom . The main contributions are as follows:1. The function and structure of Acess Memory Unit are analyzed. And the structure is researched for getting the design Methodology based the combination of Full-custom and Semi-custom is used to impletement Acess Memory.2. A 32-bit Sparse-tree adder is implemented with Full-custom way, the key techniques of the limited dynamic circuit design methodology are introduced, such as selection and design of dynamic circuits, noise immunity design and low-power design. Simulation results show that: the speed of limited dynamic circuits is optimized by 20.18% when compared to synthetic results,by 30.2% compared to fully static circuits;and power consumption is increased by 41.6%, but decreased by 52.36% compared fully dynamic circuits.3. A 32-bit dynamic high-speed left shifter is achieved based on barrel shifter structure composed of 128 tubes ,at least complete three left-shift operations. The dynamic circuits and dual-threshold technology is proposed to further enhance the shifter speed. The results show that: the dynamic shifter speed is optimized 42.86% than MUX2 structure of an synthetic results.4. The logic synthesis and physical design are achieved.The realization of hierarchical clock gating in logic synthesis stage is elaborated, and reduce power from the system level. The physical design is impletmented based flattening design ideological. It Focus on detailed layout ideas, power planning, clock tree design and timing optimization in physical design stage. Besides, timing of design is analyzed with STA method.5. The hierarchical verification of Memory Access Unit is discussed. The multiple levels of verification from the system level to circuit-level ensure the correct function of the whole design, and timing to meet. Function model extraction of custom module and fully verification stimulates are detailed analysed. The Full-custom modules are verified from the circuit to layout. The hierarchical verification results show that the longest path delay 1.4ns, meeting th 600MHz goal.