Logic Synthesis And Physical Design Of YHFT-DX

YHFT-DX is a high-performance DSP with65nm CMOS process, and has a targetfrequency of800MHz. Based on the background of YHFT-DX chip hierarchical design, thispaper makes a deeply research on the hierarchical logic synthesis, hierarchical physical designand chip-scale interconnection. It mainly includes:1) The RTL code of YHFT-DX is hierarchically compiled with the strategy of CCWSR.The devision of sub-modules and the allocation of timming constraints are deeply researched,and the low-power techniques are applied in the design of sub-modules and full-chip. The timingis meted and the power consumption is reduced at the same time. Comparing to the method offlatten synthesis, although the area of hierarchical synthesis is increased by2.5%, the dynamicpower consumption is decreased by20%and the time is reduced to the1/8of the former.2) The physical design of YHFT-DX is completed with the flow of hierarchical design, itmainly inclueds the floorplanning, power planning, devision of sub-modules and allocation oftimming constraint, synthesis and optimization of clock tree, routing and static timing analysis,etc. Taking the L1D_Top for example, the flatten physical design flow of sub-modules isintroduced. With the hierarchical design flow, the parallel ability of design is improved and thedesign period is shorted. Comparing to the flatten physical design flow, the hierarchical physicaldesign time is reduced by50%.3) The chip-scale interconnection of YHFT-DX is implemented with the method of soderbump to prepare flip-chip. The interconnection begins after the floorplan, and it’s a paralleprocess with the physical design. When the physical design is finished, the assemble of full chipwill be completed through the migration of the chip-scale interconnection. In the process ofinterconnection, a new way to speed up the interconnection is presented. With the new way, themanual work is reduced by50percent, and the maintainability is improved.4) The physical design rule verification and power analysis is done to the final layout. Afterthe completion of physical design, not only the verification tool inserted in the automatic P&Rtool is used to do the check, but also the Calibre and other specialized sign-off tools are used tocheck and verify the layout. The power consumption and IR Drop analysis is done by RedHawk,the IR Drop is controlled in less than5%by manual fixing the violation.By using the above hierarchical design method and chip-scale interconnection, theparallelism is improved and the design period is shorted. Finally, the800MHz design goal isachieved.