The Cell Synchronous Algorithms And ASIC Implementation Research In LTE-A System

In the context of large scale commercialization of 4G technology and the parties strive to achieve 5G network business in 2020,the future development of LTE-A system with long term evolutionary evolution has been the focus of attention.As the LTE-A system uses OFDM multiple access technology,timing and frequency deviation are very sensitive.In the LTE-A system,cell synchronization is one of the key processes for user carry on data communication,the user equipment obtains physical layer cell identification and system information and synchronizes with the cell for timing and frequency,so accurate cell synchronization on the user terminal receiver performance has great significance.Based on the future development of LTE-A requires low latency,high transmission,low power consumption,large convergence trend and considering the diversity of different market needs,the original cell synchronization in the algorithm still has space to improve and the hardware implementation of the chip area and power consumption also has the possibility of reduced.According to the 3GPP protocol,the synchronization algorithm and the hardware implementation considerations,how to balance the algorithms performance with the chip area,the power consumption requirements are worth studying in the algorithm and engineering realization,so the LTE-A system cell synchronization algorithms and ASIC implementation research has important practical significance.In this thesis,we mainly study the synchronization technology of the cell including the related synchronization algorithms and the hardware ASIC implementation and verification.According to the characteristics and requirements of the cell synchronization algorithm and ASIC implementation,we design a reasonable implementation scheme to meet the performance requirements,in accordance with the requirements of the project team to reduce resource loss.The following is the main content of this thesis:1.Introduce the structure of the physical layer downlink channel and the synchronization signal of the LTE-A system and introduce how the synchronization signal is generated,mapped and it's related attributes,and the basic process of cell synchronization.2.The related strategies and algorithms of cell synchronization correlation are analyzed,simulated and compared.To the PSS timing synchronization algorithm is improved,the local sequence make preconditioned frequency offset and then carry out correlation operations with PSS receiving sequence in order to reduce complexity.In the PSS timing synchronization process,we carry out a detail operation to calculate the average of two adjacent points sum power in order to reduce the length of memory storage of savings in storage resources.The effects of different timing drift values on PSS timing coarse synchronization are selected.Improve the repetition rate of the sample points of the frequency fine synchronization algorithm and increase the judgment of the effectiveness of the cell.Through the above analysis and improve,propose an appropriate algorithms for hardware ASIC implementation to achieve the design.3.The main work of this thesis is through the proposed algorithm,a detailed design of the core computing unit is given from the perspective of chip ASIC design,and the module interface,register and memory are described in detail.And then use the advanced ASIC design method to achieve the module RTL code,through the state machine reasonable design and IP multiplexing to reduce the consumption of clock resources to save area,the use of low-power chip design RTL code into the gated clock to effectively reduce power consumption.4.Finally,the method of UVM verification based on System Verilog language is used to build a module level verification platform,and all the functional points of the module are verified and validated.The area of the ASIC design is 1 200 805.674 470 52 um~2 and the power consumption is 47.054 260 3 mw.By comparison of similar design module TD-LTE-A of project team,the area of ASIC design module is 7.8%smaller than TD-LTE-A similar modules;the power consumption is 8.26%lower than TD-LTE-A similar modules.It has certain advantages in area and power consumption to meet the design requirements and application value.