Design And ASIC Implementation Of RS Encoder And Decoder For DVB

With the rapid progress of computer communication technology, the error correcting codes (ECCs) and the error control technology beign to play more and more important roles in modern information transportation and storage systems. The usage of error correcting codes can lower the bit-error rate (BER) in digital communication systems and data storage systems, and hence improves the communication quality. Reed-Solomon (RS) codes are one of the most powerful and widely used ECCs, showing the very strong capability of correcting the burst or random errors. As a result, RS codes have been widely applied in digital and mobile communication systems, data storage and digital video broadcast (DVB) systems.This thesis gives an in-depth study on RS encoding and decoding technology based on a comprehensive analysis of recent domestic and international research progress in this area. Firstly, the basic algebra theory of Galois Field (GF) and the principles of RS codes are presented. The improved Berlekamp-Massey (BM) iterative algorithm is then analyzed in detail. The modified serial inversionless BM (iBM) iterative algorithm can not only avoid the difficult inversion operations, but also lower the complexity of hardware implementations greatly by using only three GF multipliers. Secondly, the Chien-search method and the Forney algorithm are discussed and adopted to perform the error-detection and error-correction, as well as the discussions of their hardware implementations. The verification based on Xilinx Virtex5 device and the FPGA synthesis are then studied. The ASIC implementation of IP-core based RS codes is finally introduced.The major contribution of this work lies in proposing the specific RS encoding and decoding algorithm, using improved serial iBM algorithm to solve the key equation, and applying optimized pipeline structure to the RS decoding process. These technologies play a critical role on improving the efficiency of RS codes and saving the RS code-occupied resources. Because the most complicated and critical part in RS codes is the deisgn of RS decoders, a particular focus is put on the detailed design and ASIC implementation of an IP-core based RS decoder. While a RS code applicable to DVB system is proposed, some practical synthesis-oriented design and design for test (DFT) ASIC skills acquired from real engineering projects are also discussed for reference.