Research And Asic Design On Synchronization Algorithm Of Radio Broadcasting System Based On Ofdm

Taking the CMMB demodulator chip project as background, this thesis firstly researchs the theoretical basis of the OFDM mobile communication, studys the various features of the wireless channel, analyzes a variety of synchronous demodulation errors to the system caused by various effects, such as ICI and ISI caused by the symbol timing error, carrier frequency offset and sampling clock skew; By reading classical synchronization algorithm, combined with the structural features of CMMB, comparative analysis of the pros and cons of various algorithms, a suitable synchronization algorithm with the CMMB system is proposed. The algorithm uses time joint frequency domain synchronization, in the time domain, using two 2048-point to catch the coarse symbol timing and estimate fractional frequency offset; in the frequency domain, through the continuous-pilot auto-correlation first estimate integer frequency partial, and then using the continuous pilots to trace the residual carrier frequency offset and sampling clock skew.Secondly, based on the proposed algorithm, associated with the characteristic of CMMB continuous broadcasting system having less demanding on synchronization time, we bring forward an architecture of the synchronization sub system.And for which the joint fractional symbol timing offset estimation module, an integer frequency offset estimation module, the remaining carrier frequency offset and sampling clock skew tracking module, using Verilog to achieve a specific hardware circuit. When implemented in hardware, module reusing and pipelining technologies are used to reduce the consumption of the hardware area. Using the VCS simulation tool and comparing the results of fixed-point C algorithm with the verilog module, the correctness of the module-level algorithms is validated, and statistics of the RTL code coverage are reported.Finally, these sub-modules are integrated into the CMMB demodulator chip baseband system, using of EP2S180 for prototype verification and debug, the module's capabilities are validated. At the same time, testing the chip performance in a variety of channels by using of the E4438C and FADER software, the test results show that the system performance can meet to the CMMB test standard.