Design And Verification Of CELL Mapping Unit In OTN Transport Network

Today, in the expansion of the information, optical translation network businesscarries the huge transformation. As the Internet of things and the rapid development ofultra-wideband technology, as well as the mutual infiltration between different business,the traditional transport network technology in high bandwidth and multiple businesstransmission performance. The future translation network technology will furtherexpand transmission capacity and build more business oriented unified platformdevelopment two aspects.OTN usually consists of switching node and optical fibers which is used forconnecting switching node. After congregated clients’ business entering OTN, itcompletes choice in switching node and finally reachs the destination through the fibertransmission. IP switching will become the main form of the switching communicationnetwork with the development of muti-business platform in the future. Therefore, it isclearly that the obvious flow characteristics of IP how to process the switching of OTNbusiness will have great significance.The main topic of my thesis is to study how to enter IP switching net to exchangein the form of packeted data of flow swapping OTN business. For the characteristicsand application of OTN transmission net, this paper designs and implements the ODU-optical channel data unit and CELL mapping circuit, and verifies the design of thecircuit which is based on the VMM proved frame system.Firstly, this paper gives an elaborated discuss on the frame of OTN and putsforward a set of reasonable OTN exchanged cell structure. And based on the cellstructure, I put forward to an effective way of CELL maping and rate adaptation. What’smore, I put forward sharing scheme which is a kind of self-organizing block memoryand it is based on characteristics of OTN, which effectively reduce the cost of ASICchips that enhance the competitiveness of the chips.Secondly, this paper makes a detailed introduction of the feature of asynchronousmapping unit and exhaustively introduces its module partition and module functions ofdesign.Finally, this paper introduces the verification methodology of VMM and detailed introduces the module validation strategy and the simulation and verification of theVMM frame of mapping circuit verification environment to my thesis’s the design ofthe CELL mapping circuit simulation verification by System Verilog language.