Eos System Asic Chip Data Processing Module-based Authentication Method

RTL verification plays a very important role in the design of ASIC chips, which can be taped out only after fully verification. EoS ASIC achieves transmiting Ethernet data by SDH equipments, and the digital process module in the EoS ASIC is to encape/dencape data according to GFP/HDLC/LAPS protocols, which is one of the most important skills to implement EoS scheme. To completely verify the function, performance, and reliebility of digital process module in limited time, it's a must to choose the most suitable verification methodoly and plan a detailed verification scheme.In this paper, verification strategy and verification scheme are maken. In methodology, the most popular verification strategy is chosen, that is, coverage directed random testcase auto-gening technology. UT, IT, ST, FPGA test, and post-layout simulation are all done to ensure high quality. At the same time, to guarantee the software/hardware compativity, the software/hardware co-verification platform is established. The verification scheme includes testpiont abstracting, reusable verification platform establishment planning, functional coverage rate analysising. This scheme makes the verification sequencely and completely.According to the verification scheme, the EVC verification platform based on SPECMAN E is established; the random testcases are written referring to the testpoint. Then IT, ST and software/hardware co-verification are done, still DC and STA are done in the aspect of the front-end design. Finally, postlayout simulation is done and the 100% golden-netlist is taped out. This ASIC chip has already succeeded in first version. The verification not only guaranted the chip successful, but also developed a software/hardware co-verification platform, and this will make software/hardware co-development possible, which has great advantagement to decrease risk and shorten the period of chip development.