| Integrated circuit is into the deep sub-micron technology with the reduction in feature size.Parasitic effect becomes more serious,and power,timing and signal integrity of chip are faced with enormous challenges,so physical design of chip becomes increasingly important.In this paper,intelligent platform management chip as an example describes the logic synthesis and physical design flow of SOC chip.First,the paper analyzes logic libraries and timing constraint methods,and obtains a high-quality gate-level netlist through reasonable constraint.Then,start physical design of chip in the use of IC Compiler of Synopsis,the flow including floorplan,placement,clock tree synthesis and routing.Floorplan stage focuses on the PAD ring design and supply planning.Placement stage optimizes timing by global design rules and tight timing constraints.Clock tree synthesis stage makes timing violation greatly reduced throuth useful skew.Routing stage introduces the principle of cross-talk and antenna effect under deep submicron,and gets better result after insertion of redundant vias and standard fillers.Finally,the paper finish physical verification and timing verification in the use of signoff tool,and layout meets tapeout requirements.Clock frequency is 100 MHz.Power consumption is 60mW(not including analog circuits).Area is 4.86 mm * 3.76 mm. |
