Digital Back-end Design Of USB TYPE-C Interface Chip With Optimizing Floorplan And Placement

With the rapid development of integrated circuit design and manufacturing pro-cesses,chip integration and clock frequency are constantly increasing.Reliability problem of power supply network caused by parasitic parameters on interconnects and routing congestion issue cause greater challenge to the physical design of digital inte-grated circuits.Therefore,a reasonable floorplan and placement is an important part of ensuring the function and reliability of the chip in the physical implementation of digital integrated circuits.Based on the physical design and implementation of the USB Type-C interface chip,floorplan and placement of the chip are studied and optimized.Based on the theory of floorplan,floorplan of the USB Type-C interface chip was performed,in-cluding area setting,I/O cell placement,macro placement and power supply network planning.A rational analysis of floorplan was conducted to check its IR drop and electro migration.For the existing IR drop and electro migration problems,methods of widening the width of the core ring and increasing the number of power supply I/O units are adopted to reduce IR drop and electro migration.In addition,a non-uniform ladder type power mesh optimization method is proposed to improve the IR drop of the power supply network.To ensure standard cell density is uniform and the routing congestion is optimal,standard cells are placed.Clock tree is constructed by using buffers as the basic unit,and important clock synthesis first method is proposed to reduce clock skew and clock cell area.The digital back-end design of the USB Type-C interface chip was completed under the SMIC 0.18?m process.The IR drop of the power supply was reduced from the initial 23.55mV to 16.35mV,and the IR drop of the ground bounce was reduced from the initial 24.85mV to 5.21mV.The power supply IR drop and the ground bounce IR drop totally account for 1.2%of the supply voltage while less than 3%of the design requirement.The maximum current density of M4 is 2.54 A/cm~2,and the maximum current density of M5 is 5.74 A/cm~2.These meet the design requirement.Finally,the layout of chip passed various verifications.