The Study Of ASIC Backend Design Based On SOC Encounter

With the rapid development of semiconductor, Integrated circuit has been penetrated into all aspects of People’s Daily life such as modern communications, automotive electronics, medical and transportation systems. However,the development of Integrated Circuits is greatly limited by parasitic effects caused by the scaling figure size of device, the nonideal effect caused by interconnect effect such as signal integraty,IR drop and temperature inversion make the timing closure more complicate due to crossed impact among variables.At the same time,the number of logic gate in single chip reachs to several billions gates and the frequency of clock exceeds GHz or more,it has been difficult to make design clousre only by improving process technoloy. Therefore,how to reduce the design’s cycle has become the main research content of physical design. Back-end design is not just the mastery and application of EDA tools but needs to develop a targeted design flow for specific design,which plays a key role in the success of chip. In this paper, logic synthesis,design for test,static timing analysis and backend design are studied carefully and complete logic synthesis,timing verification and physical design of the 8 bit RISC_MCU based on TSMC 0.18 um 1P 6M CMOS process. The author’s major contributions are outlined as follows:1. Logic synthesis has been studied.Focus on the study of the logic synthesis constrains and operating conditions,the timing constraint method with multiple clock domains existing and logic synthesis compilation as well as optimization strageties are disscussed briefly.Then the operating condition and constraints of 8 bit RISC_MCU are defined to make the desgin to be synthesized to generate netlist and netlist quality evalution principle is summarized, Logic equivalence check by Formality is made between netlist and RTL code to verify the consistence of logic function.2. Design for Test has been studied. The theorical knowledge about Design for Testi is firstdisscussed,the emphasis is put on the test timing,test rules and test model.A test-ready compile of 8bit RISC_MCU is run for checking test fault coverage and inseting scan chain. Two diffirent methods are analyzed and adopted to improve the test coversge from primary test coverage 0.46% to 99.97% to meet the test coverage requirement.Finally scan chain is inserted and test protocol is written out for scan reordering in backend design flow.3. Static timing analysis has been studied.The principle of static timing analysis is presented in detail,the difference between parasitic format spef and standard delay format sdf is analyzed and the respective purpose are specified. Furthermore, the partition of timing path and the timing analysis modes: single,bc_wc and OCV are studied and the more importance is attached on the research on the content of OCV and common path pessisim. Finally, OCV analysis mode is used to verify the timing of RISC_MCU with CPPR feature successfully.4. Physical design has been studied. The entire backend design flow from data preparation to routing is discussed specifically. The content of Floorplan and its result having the effect on the convergence of design and the reorder of scan chain of design are also evaluated.In the phase of clock tree synthesis,clock tree constraint file is first written,then verified by the use of command analyze Clock Tree Spec before real CTS to check the rationality of clock tree constraint file.Multi-Corner Multi-Mode is discused and used for timing verification and optimization till the end of routing. Finally,formal verification is made between post-layout netlist and pre-layout and the result is successful.