A Method Of Logic Synthesis And Place-and-route For Power Balanced

With the development of microelectronic, computer science and technology,cryptology and so on,cryptographic chip plays an important role in the information system. Cryptographic chip has become the object of malice attacks,for it is always the key of security control. The channel attacks technology which is aimed to get the keys of cryptographic chip analyzed side information of the measurable power and electromagnetism, avoid the cryptographic security issue that is based on account complication.The method of power balanced is an effective means to resist power attack. The power value of dual rail power balanced method is unrelated with the transition of input signal, thereby it can keep the balance of power. The structure of dual rail power balanced cells is so different with the traditional standard cell that the existing business EDA tools can’t directly support its back-end manipulation. For the sake of using the existing mature EDA tools furthest to achieve the back-end manipulation of dual rail logic and resisting the side-channel technology,this thesis study the method of design compiler and routing about power balanced logic. The innovations of this thesis are as follows:1. For the question of existing mature EDA tools can’t support the design complier about dual rail logic, this thesis proposed a method that is replace the information of traditional standard cell by the information of dual rail power balanced cell. By this method,we can form a dummy single rail cell database file and use the existing mature EDA tools furthest to achieve the back-end manipulation of dual rail logic.2. For the question of symmetry routing about dual rail signal, This thesis proposed a dual rail signals routing method. This method used the user-defined routing rules and mature EDA tools to routed fat wires based single rail. Then using scripts to deal the LEF files automatically, which included the result information of routing. After processing, the single rail signals will be expanded to dual rail signals. Finally, the GDSII data of the balanced dual rail routing will be formed.3. Realized the common semi-custom design flow that faced power balanced modules, from compile the RTL level codes and logic synthesis to routing. Both extracting the LEF and LIB files of dual rail cells and constructing the database files,which is used in logic synthesis and routing, are this paper’s jobs. Otherwise, this paper take a power module in the AES arithmetic, for example, to validate the usability of these methods. The result of SPICE simulation show that the waveforms of power’s current are almost superposition although in different inputs. And the value of NED parameter, which is expressed the circuits’ ability of resisting power attack, is 0.09834.The module has highly achieved the character of power balanced.