Research On The Algorithm And Methodology Of Integrating High Level Synthesis And Floorplan

As the feature size of Integrated Circuits (IC) steps into deep sub-macron level, the progress of manufacture technology challenges the traditional design methodology of ICs. With the scale of integrated circuits keep increasing, the physical parasitic effect has been playing the dominant role in total performance of circuits. In traditional design flow, because the High Level Synthesis (HLS) phase and Floorplan phase are separated, numerous design iterations have to be taken to find a good result, which is known as Design Closure problem. To solve this problem, integrating HLS and Floorplan has to be engaged. In this thesis, the methodology and algorithms of integrating HLS and Floorplan are both researched. The major contributions of this thesis are:A new methodology of integrating HLS and Floorplan for circuit performance optimization is presented in this thesis. Because of the computational complexity of HLS and Floorplan (both NP-HARD problems), the new methodology devides the whole design flow into two phases: a"fast scan"phase and a"detail optimization"phase. This kind of division is not based on the functionality of each phase, but the theorial analysis of the new searching space. In this way, HLS and Floorplan are integrated in deeper level, and the constringency of the searching procedure on this new searching space can be guaranteed. The software model for this new methodology is also implemented. The VHDL descritption of a FIR filter and an ELLIPF circuit are used to test the methodology. The experimental results show that, constract to traditional design methodology, the performance of the final circuit is optimized by 21%.A new algorithm for high level re-allocation after flooplan is also presented in this thesis. In this algorithm, the length of interconnect wires are simulated as a virtual force acted on operations, and the interconnect delay is optimized by a"simulated force balance"procedure. Constract to the logic re-synthesis procedure and the layout optimization procedure, the algorithm can optimize the delay ofinterconnect wires in different control steps seperatedly. In this case, the optimization procedure can be more subtle. A FIR filter circuit and real world IDCT decoder circuit are used to test the new algorithm; the experimental results show that the total delay of the circuit was optimized by 8%.A new algorithm for high level re-scheduling after floorplan is presented in this thesis. In this algorithm, the delay of total circuit is optimized by relaxing constraints for interconnect wires, instead of changing the length of interconnect wires. Also, the algorithm can cooperate with the re-allocation algorithm for a further circuit performance optimization. The expertimal results show that the total delay of the circuit can be optimized by 11.5%.