A Memory-logic Separated 3D Chip Physical Design Method

With the development of very-large-scale integrated circuit technology,the degree of chip integration and scale has increased dramatically.The development of integrated circuit scaling is approaching the limit,and the development of 3D integrated circuits,which is most likely to reduce the interconnection delay and improve circuit performance,has been paid more and more attention.As a new design method of system-level architecture,3D integrated circuits are used to provide vertical communication among multiple wafers(Dies)through the TSV(Through-silicon-via)technology.It can overcome the limitation of feature size and greatly improve the density of the transistors on chip.However,there is no uniform standard for the physical design process of 3D integrated circuits,and the research in EDA field is not sufficient.Therefore,the research in physical design method of 3D integrated circuits based on EDA tools has become the key to promote the development of 3D integrated circuits.In this paper,the physical design of 3D integrated circuit is studied.In this paper,the physical design method of integrated circuit is analyzed.Aiming at the layout and routing process of the physical design of 3D chip,this paper presents a physical design method of separating the memory units and the logical units to convert 2D chips into 3D chips.In this paper,the layered design of netlist which converts 2D chips into 3D chips is realized.After the logic synthesis of the design and the access to the gate-level netlist,a new algorithm for stripping the memory netlist is proposed.It splits the memory units and the logical units in the netlist and realizes the layering of the netlist in the process of converting 2D chips into 3D chips.In this paper,the position optimization of the upper memory units is realized.Aiming at the problem of floorplan and routing in the upper memory units,this paper proposes a coordinate algorithm for determining the position of the memory units.A coordinate correction algorithm is proposed to solve the overlap problem of the upper memory units and optimize the position of the upper memory units.In this paper,the physical design of the upper and lower layers in 3D chip is realized.In the design process,the TSV cells are added to upper layer,and the PAD cells corresponding to the TSV cells are added to lower layer.The interconnections between upper and lower layers are achieved by implementing floorplan and routing separately with 2D physical design EDA tools.This paper proposes a new method for the physical design of 3D chips.And the design of this paper can be completed in 2D physical design EDA tools.This process is compatible with the 2D physical design process.Therefore,the research of this paper has a high reference meaning in the research and application of the physical design of 3D IC.