Research On Parallel Timing Synchronization Technology In QAM Demodulation Data

High-speed digital transmission is more and more important to people’s lives.The current communication infraarchitecture and communication rates can not keep up with the ever-increasing demand for high-speed digital information.Digital signal parallelization is a trend of processing,the parallel demodulation processing of the communication system is important,and timing synchronization is an important part of the demodulation process.This dissertation starts from the parallel architecture of demodulation,researches the parallel timing synchronization,and combines FPGA hardware to implement and verify the designed modules.First of all,this dissertation analyzes the existing parallel demodulation architecture.Because the APRX architecture uses less resources and has lower implementation complexity,the APRX architecture is chosen as the parallel architecture for demodulation.Based on the APRX architecture,the communication scheme is designed.Through the theoretical analysis of modem,the parameters such as modulation mode and IF are determined.The frequency domain matched filtering method is optimized to solve the use of logic resources.Secondly,through the analysis of timing synchronization theory,the O&M timing error detection algorithm is selected,and the parallel implementation of O&M error detection algorithm is designed in detail.Combined with the APRX frequency-domain architecture,this dissertation chooses the frequency domain correction method of timing frequency offset,and thus relived the use of resources.The correction of timing offset is designed to be achieved by deleting or holding the sampling points.Then,combined with MATLAB simulation tools,the detailed parameters of the parallel architecture are simulated to verify the correctness of the parallel architecture.According to different timing frequency offset and phase offset,MATLAB simulation is carried out to realize the effect of timing synchronization algorithm,and the appropriate O&M error detection algorithm parameters are selected.Finally,according to the hardware architecture of the parallel architecture chosen,FPGA was selected as the basic hardware for digital processing.Combined with FPGA hardware,write Verilog HDL code to achieve parallel logic timing synchronization code.The function simulation of the code verifies the correctness of parallel processing of the timing synchronization logic code in parallel.Finally,board-level verification is performed to meet the BER performance of 10-6 when the signal-to-noise ratio is 16 dB under the condition of timing offset less than 200 ppm.It is verified that the timing synchronization function meets the design requirements.