Research And Realization Of Timing Recovery In Broadband Variable Rate Modem

In recent years, broadband variable speed satellite communication system has huge demands in civilian areas and military areas, and the variable rate modulation and demodulation is the key technique which should be firstly solved in the implementation of broadband variable speed satellite communication. The selection of this project is based on civilian space advanced research item for the twelfth five-year plan——the design and realization of the satellitic broadband variable speed modem. The limitations of the satellitic hardware resources restrict the possibilities to set separate modem module individually for each user. Thus, the research on structure, which can realize the single-channel high-speed and multi-channel low-speed symbol synchronization, has theoretical and engineering practical significance to implement the broadband variable speed modem. The project clearly puts forward the optimized design requirements of the modem on realization of high-speed forward timing synchronization and implementation of multiple low-speed data timing synchronization. The high-speed and multi-user requirement greatly increase the difficulty of implementation of modem.From the current view, all-digital modem adopts the high-speed data transmission system. In digital communication systems, the symbol synchronization is the core processing part of signal demodulation, and the time cost in symbol synchronization and the accuracy of synchronous results can both restrict the performance of the whole communication system. With the background of realizing broadband variable speed modem, this paper mainly analyzes and discusses the important issues in all-digital communication.First of all, it thoroughly analyzes and studies the variable rate timing synchronization in variable speed modem, expounds systemically the theory of timing synchronization, highlights the timing synchronization multiplexing principle in variable rate modem implementation and its implementation, and conducts a comprehensive simulation and analysis based on digital channelized theory, and realize in hardware circuit.Then, this paper makes a theoretical analysis about timing synchronization module, studies in depth on this subject with background of all kinds of requirements in practical application and describes the Gardner timing recovery loop and models of each structure from the system, and takes relevant theories of digital phase-locked loop as basis and conducts a comprehensive simulation on the parameters of the system. And realize the timing error detector in hardware circuit.At last, the paper in view of the various restrictions of Gardner method in multi-user data processing, some improvement measures and plans can provide some references to improve the system performance in hardware implementation.