Study And Implementation Of Timing And Carrier Synchronization For High Data Rate Demodulation

With the rapid development of digital communication technology, the demand for very high data rate is growing as the way of Moore’s law. In recent years, serial demodulation mode can hardly meet the requirement of high data rate demodulation.Therefore, researches on high data rate parallel demodulation architecture and critical technologies such as parallel timing synchronization, parallel carrier synchronization,which will provide theoretical foundation and reliable methods of implementation for high data rate demodulation, should be urgently conducted.According to the design requirements, a parallel frequency-domain demodulation architecture based on APRX(All-Digital Parallel Receiver) is proposed. Furthermore,the workflow of high data rate demodulator is shown in detail. Simultaneously, timing synchronization and carrier synchronization as two key technologies are analyzed.Compared with early-late door and Gardner, O&M is finally chosen to be the implemented algorithm of timing synchronization because of unbiased estimation and simplicity of implementation on FPGA. And the simulation result of the symbol accumulation length is investigated as well as derivation for the FPGA implementation of timing-error estimation and correction in frequency domain. What’s more, the logic circuit and its simulation are proposed. MATLAB Simulations show that the parallel timing synchronization algorithm is not sensitive to the carrier frequency and phase offset, and can realize timing synchronization with jitter of 0.1% after capture. Also, this algorithm is suitable for QAM/PSK modulated signal.For carrier synchronization, based on the traditional decision-director(DD)algorithm and the polarity decision algorithm, a structure which switches between two modes is proposed. The algorithm combines with rough frequency capture mode(PFD,Phase Frequency Detector) and accurate phase tracking mode(PD, Phase Detector)solves the contradiction between phase jitter and convergence speed. In the logic design,the circuit of the gain adjustment is added to normalize the amplitude of the signal. As for the parallel structure of carrier synchronization, a simple implementation of the PD decision module for QAM/PSK is discussed, the logic circuits and simulations of the modules for PD decision, DDS, state-change are derived. The characteristic of the reformed duel-mode carrier recovery algorithm which have larger acquisition range andless phase jitter is verified in the simulation. The algorithm is suitable for both QAM and PSK modulated signal.Finally, the testing platform of high data rate demodulation and the key devices are introduced. The function tests of parallel timing and carrier synchronization are conducted under the condition of the MATLAB fixed-point input and the actual A/D sampling data input. The results shows that parallel timing synchronization can acquire the symbols with maximal SNR, which are fixed in the first position; parallel carrier synchronization can capture frequency offset ranging from ?10k Hz to ?1MHz,meet the design requirement. The feasibility of parallel timing and carrier synchronization are verified.