The Research And Implementation Of Symbol Variable Rate Timing Synchronization For Wideband Satellite

It is inevitable for satellite communication systems to provide high-bandwidth communication services.To meet different business needs of ground terminals,highthroughput satellites with larger bandwidth and higher spectral efficiency will be one of the development directions of satellite communication systems and bring about a geometric increase in transmission speed.Traditional serial processing methods are limited by the clock frequency of Field Programmable Gate Array(FPGA),which is difficult to achieve highspeed data demodulation.Therefore,it is urgent to reaserch a parallel demodulation technology in high-speed processing.Based on the study of all-digital demodulation technology,this thesis proposes a kind of timing synchronization scheme that is suitable for multiple modulation and variable symbol rate based on Alternative Parallel Receiver(APRX)architecture,then the multi-rate conversion and timing synchronization technology are studied and implemented in FPGA.Firstly,the basic theory and architecture of the existing all-digital demodulators are introduced.Based on the study of APRX,this thesis proposes a demodulator timing synchronization scheme which is suitable for symbol rate between 0.195 Msps and 800 Msps and various modulation such as Quadrature Phase Shift Keying(QPSK)and 64 Amplitude Phase Shift Keying(64APSK)by analyzing key algorithms in integer multiple sampling rate conversion and timing synchronization,which can meet the design specifications.Secondly,aiming at the problem that the existing demodulator is difficult to demodulate signals of different symbol rate at a fixed sampling rate,the cascade decimation filtering method is proposed to achieve 1,4,16,64,256,1024 integer multiple sampling rate conversion at the front of the demodulator,then the design parameters and implementation structure of all filters are analyzed.For filter’s FPGA implementation,the implementation of the parallel frequency domain filter is simplified based on the frequency domain multiplication corresponding to the time domain convolution theory;based on the polyphase decomposition theory and equivalent transformation structure,the multiplication efficiency of the latter stage filters are improved by multiplexing.The simulation and implementation results show that the scheme can correctly realize the integer multiple downsampling transformation and occupy less hardware resources.Thirdly,for the problem of existing timing synchronization technology processes data at a low rate and is difficult correcting a wide range of sampling frequency offset,a high-speed timing synchronization scheme with joint parallel resampling is proposed.Through the research of digital resampling theory,this thesis proposes using Farrow interpolator structure to realize 1～4 times fractional sampling rate conversion,then analyzes the FPGA implementation of parallel resampling device in detail and completes the simulation verification.While designing the timing synchronization loop,the parallel implementation of the O&M(Oerder M & Meyr H)algorithm is analyzed and deduced,then we propose using dual feedback loops to complete timing correction based on the principle of timing phase/frequency offset correction.The simulation results show that the scheme can support different modulation and any fractional upsampling between 4 and 16.The Error Vector Magnitude(EVM)between the recovered signal and the ideal signal is less than 5%.Finally,the FPGA implementation of the scheme proposed in this thesis is verified on the xc7vx690tffg1761-2 of Xilinx Virtex-7 series chip.The results show that the symbol timing synchronization scheme suitable for variable symbol rate in broadband satellite is able to reach the highest symbol rate of 800 Msps and process signals with 1GHz bandwidth.The processed signal satisfies EVM less than 5%,which has practical engineering significance.