Research And Implementation Of Low Jitter Timing Synchronization Technology Based On GA-TED

With the rapid development of digital information society,the demand for largecapacity multimedia services is growing,therefore,the challenge of wireless digital communication technology is also increasing: larger communication capacity,higher bandwidth utilization,more reliable transmission stability and faster communication rate.Quadrature Amplitude Modulation(QAM)technology is widely used in wireless digital communication systems because of its strong noise resistance and high band utilization.As the most important and complex part of the entire communication system,the design of digital receiver directly affects the performance of the entire communication system.And the timing synchronization module is an essential part of the digital receiver before the symbol decision.Timing synchronization technology is mainly used to correct the timing deviation caused by different clock sources between the transmitter and the receiver,in order to ensure that the signal sampling process can be carried out at the best sampling time,and to reduce the symbol error rate of the communication transmission.This dissertation will focus on the timing synchronization technology of the high-order QAM digital communication receiver.Firstly,this dissertation combs the basic theory of timing synchronization technology.Through the research and analysis of the implementation principle of the traditional Gardner timing synchronization algorithm,this dissertation expounds the main reason of timing jitter in the timing synchronization loop: the out-of-band Gaussian noise and the loop self-noise caused by the non-zero intermediate sampling value of high-order QAM signal.Therefore,starting from the symbol hopping characteristics of 64 QAM signal,this dissertation modifies the traditional Gardner timing error estimation formula to reduce the loop self noise.In addition,according to the frequency spectrum characteristics of the timing error signal,an optimized prefilter is added to reduce the out-of-band Gaussian noise.Under the limited input conditions,the design of low jitter timing synchronization scheme based on optimized timing error detector and optimized prefilter is completed.Then,the simulation model of the improved low jitter timing synchronization scheme is built,and the feasibility and effectiveness of the scheme are verified by functional simulation and performance comparison simulation.The functional simulation results show that the improved low jitter timing synchronization scheme can effectively correct the timing deviations above 500 ppm.Through the analysis of the loop convergence curve,constellation diagram and eye diagram in the performance comparison simulation results,it is verified that the improved timing synchronization scheme can reduce timing jitter by 75% compared with the timing synchronization scheme without jitter elimination.Finally,this dissertation uses Verilog HDL hardware programming language to implement the low jitter timing synchronization scheme based on FPGA,and verifies the feasibility and effectiveness of the scheme on the board-level communication platform based on AD9371 and XC7A200T-FBG676-2.The experimental results show that the low jitter timing synchronization scheme based on optimized timing error detector and optimized prefilter can effectively correct the timing deviation above 500 ppm at 200 Mbps data rate,which meets the design requirements of the dissertation.