Design Of Dynamic Parallel Operation Timing And Counting Control Module In PLC Based On FPGA

Timer, counter and high-speed counter is the soft devices commonly used in the PLC user program design. The subject applicate the characteristics of FPGA parallel operation, analysis the functional requirements of PLC timer, counter and high-speed counter, design the system structure of dynamic parallel operation timing and counting control module for PLC system based on ARM+FPGA architecture. The timing and counting control module can realize the parallel PLC timing, counting and high-speed counting function. At the same time, the timer control module and counter control module is reconfigurable, The total number of its internal timer or counter can be changed according to the specific engineering application. Achieve a flexible configuration of FPGA resources. The Subject basically achieved the following results:(1)Completed the design of the sequence of reading and writting and the communication protocol between the central controller and the timing and counting control module. Designed the communication data format in the instruction form according to the control requirements,.(2)Completed the design of the timer control module. The module is composed by 7 functional modules which the port read-write controller, the address mapping memory of timer, the timing memory, the 1KHz pulse generator, the instruction actuator of timer, the timing controller and timing results upload controller are. With 1ms as the basic timing unit, it can independently perform the timing operation after the initialization, Using the address mapping memory sequentially stores the number of timer that is used by PLC user program, only the timers that be used by PLC user program can perform the timing operation, it can mprove the efficiency of PLC timing.(3)Completed the design of the counter control module. The module is composed by 4 functional modules which the port read-write controller, the address mapping memory of counter, the instruction actuator of counter, the counting current value memory are. It can judge the on-off state of the counter drive according to instructions and performs counting operation. Using the address mapping memory sequentially stores the number of counter that is used by PLC user program, only the counters that be used by PLC user program can perform the partial reset operation, it can improve the processing speed of partial reset instruction.(4)Completed the design of the high-speed counter control module. The module is composed by 6 functional modules which the port read-write controller, the address mapping memory of high-speed counter, the high-speed counter controller, the instruction actuator of high-speed counter, the high-speed counter upload controller, the pulse input selection controller are. According to the design rules, it can independently distribute the pulse input port and set the work mode and perform the counting operation on the counting pluse. Using the address mapping memory sequentially stores the number of high-speed counter that is used by PLC user program, it can solve the contradiction that high speed counter unit less than counter number.(5)The timing simulation test and board-level debugging show that the timing and counting control module can realize its function. The timing error of timer control module within 0.1ms or less; when the counter control module using 235 counters at the same time, the maximum counting frequency is 4.88KHz; when the high-speed counter control module’s work mode is the one-phase input, the maximum counting frequency is 16.66 MHz, when the high-speed counter control module’s work mode is the two-phase input, the maximum counting frequency is 8.33 MHz.