Research On Demodulation Technique And Its Implementation For2Gbps High Speed Communication

As the development of communication technology in decades, demand for very highdata rate wireless communication in all areas is growing rapidly, from several hundredMegabits per second (Mbps) to multi-Gigabits per second (Gbps). Research shows thatdata rates of around5-15Gbps will be required in next ten years. However, existing com-munication systems cannot provide data rates that are high enough to meet the increasingrequirement in high-speed data transmission. This thesis conducts a research on highdata rate parallel demodulation and its FPGA implementation, looking forward to makebreakthrough in the critical issue of high data rate demodulation, such as parallel demod-ulation architecture, parallel timing synchronization, parallel carrier synchronization andparallel adaptive equalization.First, this thesis improves APRX parallel demodulation architecture to a universalcomplete high-speed fully parallel demodulation architecture. Based on frequency do-main matched fltering and timing phase error rotation, this architecture can easily im-plemented to demodulate modulated signal as high as multi-Gbps with very low clockfrequency and low hardware cost. In the thesis, we design the kernel of the architec-ture, a parallel frequency domain matched flter, and simplifes its parallel process. Boththeoretic analyzing and simulation demonstrate the efectiveness of the architecture.Second, this thesis proposes parallel timing synchronization algorithm, which con-sists of phase shift based approach to timing frequency ofset correction and frequencydomain timing phase ofset correction. The algorithm can avoid feedback regulation forADC clock and complicated interpolation, since it can be realized simply through in-dex transformation and multiplication. Simulations show that the algorithm can achievetiming synchronization with less than0.5dB SNR loss.Third, by introducing delay relaxation into relaxed look-ahead adaptive flter, thethesis develops a short convolution based, efective pipelined parallel implementationstructure of adaptive CMA blind equalization algorithm. FPGA implementation and sim-ulations of the algorithm are also conducted.Moreover, this thesis improves Phase and Frequency Detector (PFD) based on ringwindow instead of rectangle window in previous work. Combining PFD and phase do-main digital PLL, the thesis presents a ring window-based all-phase domain Decision- Directed PLL for carrier synchronization. On account of its parallel realization, the thesisdesigns a simple but efective mean-equivalent-compensation-based structure, and furtheraccomplishes its FPGA implementation. The fxed-point simulation on the whole systemshows that the demodulation performance loss of the parallel demodulation architectureis just less than1dB.Finally, based on the proposed demodulation architecture and algorithms, the thesisdevelops a high data rate demodulator prototype, the parallel demodulation architectureand algorithms are implemented on the prototype. The performance test of the prototypeindicates that, without channel code/decode, the overall SNR loss of the prototype is lessthan2dB, which validates the efciency of the proposed demodulation architecture andalgorithms. Wireless communication experiments of the prototype on140GHz, at thedistance of35m,500m and1.5km are also conducted. The achieved BER is down to theorder of1010,109and107separately.