Research On Parallel Carrier Recovery Technology In QAM Demodulation Data

With the increasing demand of high-speed broadband communication and the limited rate of digital communication system by the maximum rate of FPGA,the parallel processing technology is becoming more important in the process of realizing high-speed communication demodulation,in which carrier recovery is one of the core issues to achieve.Based on the parallel processing technology,this paper focuses on the design and implementation of QAM demodulation parallel architecture carrier recovery module.Firstly,the research on 16 QAM demodulation parallel architecture carrier recovery technology is carried out in the background of point-to-point transmission application of wireless communication.Using a collection of high precision,saving spectrum resources,blind reception and other characteristics of the feedback structure.The combination of polarity decision algorithm has the advantages of fast capture speed and high accuracy of convergence decision(DD)algorithm.The method of time automatic conversion is used to realize the combination of capture and DD algorithm.Secondly,the algorithm of time-domain parallel carrier recovery key module is analyzed by using single-channel high-speed ADC and time domain parallel processing structure,and the scheme is designed.The structure and related algorithms of parallel NCO module and matched filter module are analyzed emphatically.The carrier recovery design of 100 Mbps bit rate modulation signal is completed by 4-way parallel structure.In the design of the forming filter and matched filter in the communication system,the anti-symbol interference effect is analyzed by using the root-raised cosine roll-off filter.Then,complete the parallel carrier recovery fixed-point simulation by combing Simulink with System Generator simulation tool.The simulink is used to design the 16 QAM modulation signal with the bit rate of 100 Mbps and the intermediate frequency of 100 MHz.Then,the simulation design of parallel carrier recovery is carried out,and the relevant parameters of each module are determined,and the simulation of parallel carrier recovery is completed.Finally,the hardware implementation and debug verification and analysis of parallel carrier recovery are completed.Using Xilinx's Artix-7 series FPGA,complete the hardware logic Verilog code preparation.Combined with Modelsim complete the logic of the hardware circuit simulation,and completed the timing of the signal synchronization,DD algorithm to provide synchronous clock.According to board timing requirements,FPGA timing analysis and design.The experimental results show that the overall frequency offset acquisition range is-2.59 MHz ~ 2.62 MHz,the phase capture range is-pi / 6 ~ pi / 6,the capture bandwidth is MHz,and the synchronization is based on the experimental results.Bandwidth MHz,fully meet the design requirements.The design of the test results can be seen to complete the parallel carrier phase-locked,the feedback signal tends to converge,the output waveform is reasonable,the output 4-level eye diagram ideal,constellation is correct,successfully achieved 100 Mbps bit rate under 4 Design of Domain Parallel Carrier Recovery.